Interface design for rationally clocked GALS systems

Proceedings - International Symposium on Asynchronous Circuits and Systems

Volumn 2006, Issue , 2006, Pages 160-171

  Mekie, Joycee ^a   Chakraborty, Supratik ^a   Venkataramani, Girish ^b   Thiagarajan, P S ^c   Sharma, D K ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY BOMBAY   (India)

^b CARNEGIE MELLON UNIVERSITY   (United States)

^c NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT THEORY; COMPUTER SYSTEM RECOVERY; INTERFACES (COMPUTER); NETWORK PROTOCOLS; PROBLEM SOLVING; SYNCHRONIZATION;

DELAYAUGMENTED NETCHARTS; GENERIC INTERFACE; INTERFACE CIRCUITS; SYNCHRONIZATION MECHANISMS;

LOGIC DESIGN;

EID: 33749590929     PISSN: 26431394     EISSN: 26431483     Source Type: Conference Proceeding    
DOI: 10.1109/ASYNC.2006.19     Document Type: Conference Paper

References (12)

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