Automatic layer-based generation of system-on-chip bus communication models

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 26, Issue 9, 2007, Pages 1676-1687

  Gerstlauer, Andreas ^a,b   Shin, Dongwan ^a,b   Peng, Junyu ^a,b   Dömer, Rainer ^a,c   Gajski, Daniel D ^a,b  

^a IEEE

^b UNIVERSITY OF CALIFORNIA   (United States)

^c University of California at Irvine   (United States)

Author keywords

Communication synthesis; Embedded systems; Heterogeneous multiprocessor system on chip (MPSoC); System level design; Transaction level modeling (TLM)

Indexed keywords

AUTOMATION; COMMUNICATION CHANNELS (INFORMATION THEORY); EMBEDDED SYSTEMS; MATHEMATICAL MODELS; SPACE RESEARCH; SYSTEMS ANALYSIS;

COMMUNICATION SYNTHESIS; HETEROGENEOUS MULTIPROCESSOR SYSTEM-ON-CHIP (MPSOC); SYSTEM-LEVEL DESIGN; TRANSACTION-LEVEL MODELING (TLM);

MICROPROCESSOR CHIPS;

EID: 34548233318     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2007.895794     Document Type: Article

References (41)

1. T. Grötker, S. Liao, G. Martin, and S. Swan, System Design With SystemC. Norwell, MA: Kluwer, Mar. 2002.
2. D. D. Gajski, J. Zhu, R. Dömer, A. Gerstlauer, and S. Zhao, SpecC: Specification Language and Design Methodology. Norwell, MA: Kluwer, 2000.
3. G. Schirner and R. Dömer, "Quantitative analysis of transaction level models for the AMBA bus," in Proc. DATE, Mar. 2006, pp. 1-6.
4. M. Coppola, S. Curaba, M. Grammatikakis, and G. Maruccia, "IPSIM: SystemC 3.0 enhancements for communication refinement," in Proc. DATE, Mar. 2003, pp. 106-111.
5. W. O. Cesário, D. Lyonnard, G. Nicolescu, Y. Paviot, S. Yoo, and A. A. Jerraya, "Multiprocessor SoC platforms: A component-based design approach," IEEE Des. Test Comput., vol. 19, no. 6, pp. 52-63, Nov./Dec. 2002.
6. K. van Rompaey, D. Verkest, I. Bolsens, and H. D. Man, "CoWare: A design environment for heterogeneous hardware/software systems," in Proc. Eur. Des. Autom. Conf., 1996, pp. 252-257.
7. T-Y. Yen and W. Wolf, "Communication synthesis for distributed embedded systems," in Proc. ICCAD, Nov. 1995, pp. 288-294.
8. M. Gasteier, M. Munch, and M. Glesner, "Generation of interconnect topologies for communication synthesis," in Proc. DATE, Mar. 1998, pp. 36-42.
9. M. Gasteier and M. Glesner, "Bus-based communication synthesis on system-level," in Proc. ISSS, Nov. 1996, pp. 65-70.
10. R. B. Ortega and G. Borriello, "Communication synthesis for distributed embedded systems," in Proc. ICCAD, Nov. 1998, pp. 437-444.
11. K. Lahiri, A. Raghunathan, and S. Dey, "Efficient exploration of the SoC communication architecture design space," in Proc. ICCAD, Nov. 2000, pp. 424-430.
12. W. Klingauf, H. Gädke, and R. Günzel, "TRAIN: A virtual transaction layer architecture for TLM-based HW/SW codesign of synthesizable MPSoC," in Proc. DATE, Mar. 2006, pp. 1-6.
13. I. Bolsens, H. D. Man, B. Lin, K. V. Rompay, S. Vercauteren, and D. Verkest, "Hardware/software co-design of the digital telecommunication systems," Proc. IEEE, vol. 85, no. 3, pp. 391-418, Mar. 1997.
14. D. Lyonnard, S. Yoo, A. Baghdadi, and A. A. Jerraya, "Automatic generation of application-specific architectures for heterogeneous multiprocessor system-on-chip," in Proc. DAC, Jun. 200.1, pp. 518-523.
15. W. O. Cesario, A. Baghdadi, L. Gauthier, D. Lyonnard, G. Nicolescu, Y. Paviot, S. Yoo, A. A. Jerraya, and M. Diaz-Nava, "Component-based design approach for multicore SoCs," in Proc. DAC, Jun. 2002, pp. 789-794.
16. K. Lahiri, A. Raghunathan, and S. Dey, "System-level performance analysis for designing on-chip communication architectures," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 20, no. 6, pp. 768-783, Jun. 2001.
17. X. Zhu and S. Malik, "A hierarchical modeling framework for on-chip communication architectures," in Proc. ICCAD, Nov. 2002, pp. 663-670.
18. M. Lajolo, C. Passerone, and L. Lavagno, "Scalable techniques for system-level co-simulation and co-estimation," Proc. Inst. Electr. Eng. - Computers Digital Techniques, vol. 150, no. 4, pp. 227-238, Jul. 2003.
19. SV : An extension of SystemC for mixed multi-level communication modeling and interface-based system design," in Proc. DATE, Mar. 2001, pp. 26-32.
20. R. Pasko, S. Vernalde, and P. Schaumont, "Techniques to evolve a C++ based system design language," in Proc. DATE, Mar. 2002, pp. 302-309.
21. M. Sgroi, M. Sheets, M. Mihal, K. Keutzer, S. Malik, J. Rabaey, and A. Sangiovanni-Vincentelli, "Addressing the system-on-a-chip interconnect woes through communication-based design," in Proc. DAC, Jun. 2001, pp. 667-672.
22. L. Benini and G. D. Micheli, "Networks on chips: A new SoC paradigm," Computer, vol. 35, no. 1, pp. 70-78, Jan. 2002.
23. A. Jantsch and H. Tenhunen, Eds., Networks on Chip. Norwell, MA: Kluwer, 2003.
24. Reference Model of Open System Interconnection, 2nd ed., International Organization for Standardization, 1994, ISO/IEC 7498 Standard.
25. J. Hu and R. Marculescu, "Energy- and performance-aware mapping for regular NoC architectures," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 24, no. 4, pp. 551-562, Apr. 2005.
26. S. Murali and G. D. Micheli, "SUNMAP: A tool for automatic topology selection and generation for NoCs," in Proc. DAC, Jun. 2004, pp. 914-919.
27. U. Y. Ogras and R. Marculescu, "Energy- and performance-driven customized architecture synthesis using a decomposition approach," in Proc. DATE, Mar. 2005, pp. 352-357.
28. K. Srinivasan, K. S. Chatha, and G. Konjevod, "Linear-programming- based techniques for synthesis of network-on-chip architectures," IEEE Trans. VLSI Syst., vol. 14, no. 4, pp. 407-420, Apr. 2006.
29. A. Gerstlauer, D. Shin, R. Dömer, and D. D. Gajski, "System-level communication modeling for network-on-chip synthesis," in Proc. ASPDAC, Jan. 2005, pp. 45-48.
30. D. Shin, A. Gerstlauer, R. Dömer, and D. D. Gajski, "Automatic network generation for system-on-chip communication design," in Proc. CODES + ISSS, Sep. 2005, pp. 255-260.
31. D. Shin, A. Gerstlauer, R. Doemer, and D. D. Gajski, "Automatic generation of communication architectures," in From Specification to Embedded Systems Application, A. Rettberg, M. C. Zanella, and F. J. Rammig, Eds. New York: Springer-Verlag, Aug. 2005.
32. D. Shin et al., "System-on-chip modeling style guides," UC Irvine, Irvine, CA, Tech. Rep. CECS-TR-04-22 through CECS-TR-04-24, Jul. 2004.
33. A. Gerstlauer, H. Yu, and D. D. Gajski, "RTOS modeling for system level design," in Proc. DATE, Munich, Germany, Mar. 2003, pp. 130-135.
34. A. Gerstlauer et al., "System-on-chip component models," UC Irvine, Irvine, CA, Tech. Rep. CECS-TR-06-10, May 2006.
35. D. Shin et al., "C-based interactive RTL design methodology," UC Irvine, Irvine, CA, Tech. Rep. CECS-TR-03-42, Dec. 2003.
36. H. Yu, R. Dömer, and D. D. Gajski, "Embedded software generation, from system level design languages," in Proc. ASPDAC, Jan. 2004, pp. 463-468.
37. A. Gerstlauer et al., "Necessary and sufficient functionality and parameters for SoC communication," UC Irvine, Irvine, CA, Tech. Rep. CECS-TR-06-01, May 2006.
38. S. Abdi et al., "System-on-chip environment (SCE Version 2.2.0 beta): Tutorial," UC Irvine, Irvine, CA, Tech. Rep. CECS-TR-03-41, Jul. 2003.
39. Digital Compression and Coding of Continous-Tone Still Images, International Telecommunication Union. (ITU), Sep. 1992, ITU Recommendation T.81.
40. Digital cellular telecommunications system; Enhanced Full Rate (EFR) speech transcoding, Final draft ed., European Telecommunication Standards Institute (ETSI), 1996, GSM 06.60.
41. C. Giridhar, Trendy Phones Incorporate Sophisticated Engineering, EDN Asia. [Online]. Available: http://www.edn.com/index.asp?layout= article&articleid=CA6290467