TRAIN: A virtual transaction layer architecture for TLM-based HW/SW codesign of synthesizable MPSoC

Proceedings -Design, Automation and Test in Europe, DATE

Volumn 1, Issue , 2006, Pages

  Klingauf, Wolfgang ^a   Gädke, Hagen ^a   Günzel, Robert ^a  

^a TECHNICAL UNIVERSITY OF BRAUNSCHWEIG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER HARDWARE; LOGIC DESIGN; QUALITY OF SERVICE; REAL TIME CONTROL;

HARDWARE ABSTRACTION LAYERS; ON CHIP COMMUNICATION NETWORK; VIRTUAL TRANSACTION LAYER ARCHITECTURE;

MICROPROCESSOR CHIPS;

EID: 34047163537     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2006.244124     Document Type: Conference Paper

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