Applying genetic parallel programming to synthesize combinational logic circuits

IEEE Transactions on Evolutionary Computation

Volumn 11, Issue 4, 2007, Pages 503-520

  Cheang, Sin Man ^a   Lee, Kin Hong ^b   Leung, Kwong Sak ^b  

^a HONG KONG INSTITUTE OF VOCATIONAL EDUCATION   (Hong Kong)

^b CHINESE UNIVERSITY OF HONG KONG   (Hong Kong)

Author keywords

Circuit design; Digital circuits; Evolvable hardware; Genetic programming (GP); Parallel programming

Indexed keywords

DIGITAL CIRCUITS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); GENETIC PROGRAMMING; OPTIMIZATION; PARALLEL PROGRAMMING;

EVOLVABLE HARDWARE; LOGIC CIRCUIT SYNTHESIZER; MULTILOGIC-UNIT PROCESSOR;

COMBINATORIAL CIRCUITS;

EID: 34547881074     PISSN: 1089778X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEVC.2006.884044     Document Type: Article

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