Multi-logic-Unit Processor: A combinational logic circuit evaluation engine for genetic parallel programming

Lecture Notes in Computer Science

Volumn 3447, Issue , 2005, Pages 167-177

  Lau, Wai Shing ^a   Li, Gang ^a   Lee, Kin Hong ^a   Leung, Kwong Sak ^a   Cheang, Sin Man ^b  

^a CHINESE UNIVERSITY OF HONG KONG   (Hong Kong)

^b HONG KONG INSTITUTE OF VOCATIONAL EDUCATION   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL CIRCUITS; COMPUTER HARDWARE; FIELD PROGRAMMABLE GATE ARRAYS; PROBLEM SOLVING;

GENETIC PARALLEL PROGRAMMING (GPP); GPP LOGIC CIRCUIT SYNTHESIZER (GPPLCS); HARDWARE PROCESSOR; MULTI-LOGIC UNIT PROCESSOR (MLP);

GENETIC ALGORITHMS;

EID: 24644454310     PISSN: 03029743     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1007/978-3-540-31989-4_15     Document Type: Conference Paper

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