Hardware evolution at function level

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1141, Issue , 1996, Pages 62-71

  Murakawa, Masahiro ^a   Yoshizawa, Shuji ^a   Kajitani, Isamu ^b   Furuya, Tatsumi ^c   Iwata, Masaya ^d   Higuchi, Tetsuya ^d  

^a UNIVERSITY OF TOKYO   (Japan)

^b UNIVERSITY OF TSUKUBA   (Japan)

^c TOHO UNIVERSITY   (Japan)

^d ELECTROTECHNICAL LABORATORY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION THEORY; HARDWARE; LOGIC DEVICES; NETWORK ARCHITECTURE; PROGRAMMABLE LOGIC CONTROLLERS; RECONFIGURABLE HARDWARE;

EVOLVABLE HARDWARE; FUNCTION LEVELS; GATE LEVELS; GENETIC LEARNING; NEURAL NETWORK APPLICATION; PROGRAMMABLE LOGIC DEVICE; REAL TIME; VLSI ARCHITECTURES;

PROBLEM SOLVING;

EID: 84958971631     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-61723-X_970     Document Type: Conference Paper

References (6)

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2. Goldberg D., Genetic Algorithms in Search, Optimization, and Machine Learning,Addison Wesley, 1989.
3. Higuchi T. et al., Evolvable Hardware with Genetic Learning, Massively Parallel Artificial Intelligence (eds. H. Kitano), MIT Press, 1994.
4. Iwata M. et al., Consideration on pattern recognition system based on evolvable hardware, ETL technical report, 1995.
5. Kajitani I. et al., Variable Length Chromosome GA for Evolvable Hardware, ETL technical report, Oct. 1995.
6. Marchal P. et al., Embryological Development on Silicon,Artificial Life IV, 1994.