Diode-footed domino: A leakage-tolerant high fan-in dynamic circuit design style

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 51, Issue 3, 2004, Pages 495-503

  Mahmoodi Meimand, Hamid ^a   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC CURRENTS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; SPURIOUS SIGNAL NOISE; THRESHOLD VOLTAGE; TRANSISTORS;

DIODE FOOTED DOMINO; DOMINO CIRCUITS; DOMINO LOGIC; DYNAMIC LOGIC; LEAKAGE TOLERANCE; NOISE IMMUNITY; POWER CONSUMPTION; TECHNOLOGY SCALING;

DIODE TRANSISTOR LOGIC CIRCUITS;

EID: 4544238634     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2004.823665     Document Type: Article

References (12)

1. P. Gronowski, "Issues in dynamic logic design," in Design of High-Performance Microprocessor Circuits, A. Chandrakasan, W. J. Bowhill, and F. Fox, Eds. Piscataway, NJ: IEEE Press, 2001, ch. 8, pp. 140-157.
2. M. Anders, R. Krishnamurthy, R. Spotten, and K. Soumyauath, "Robustness of sub-70 nm dynamic circuits: Analytical techniques and scaling trends," in Proc. Symp. VLSI Circuit, June 2001, pp. 23-24.
3. R. Kumar. (2001) Interconnect and noise immunity design for the Pentium 4 processor. Intel Technol. J. [Online], vol (5Q1). Available: http://www.intel.com.technology/itj/ql2001/articles/arthtm
4. K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, "Leakage current in deep-submicron CMOS circuits," J. Circuits, Syst. Comput., vol. 11, no. 6, pp. 575-600, 2002.
5. V. De and S. Borkar, "Technology and design challenges for low power and high performance," in Proc. Int. Symp. Low Power Electronics and Design, Aug. 1999, pp. 163-168.
6. J.-J. Kim and K. Roy, "A leakage tolerant high fan-in dynamic circuit design technique," in Proc. 27th Eur. Solid-State Circuit Conf.e, Sept. 2001, pp. 324-327.
7. L. Wang, R. Krishnamurthy, K. Soumyanath, and N. Shanbhag, "An energy-efficient leakage-tolerant dynamic circuit technique," in Proc. Int. ASIC/SOC Conf., Sept. 2000, pp. 221-225.
8. A. Solomatnikov, D. Somasekhar, K. Roy, and C.-K. Koh, "Skewed CMOS: Noise-immune high-performance low-power static circuit family," in Proc. Int. Conf. Computer Design, 2000, pp. 241-246.
9. A. Alvandpour, R. K. Krishnamurthy, K. Soumyanath, and S. Y. Borkar, "A sub-130-nm conditional-keeper technique," IEEE J. Solid-State Circuits, vol. 37, pp. 633-638, May 2002.
10. K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, "Leakage current mechanisms and leakage reduction techniques in deep-submicron CMOS circuits," Proc. IEEE, vol. 91, pp. 305-327, Feb. 2003.
11. Berkeley Predictive Technology Model. Univ. Berkeley, Berkeley, CA. [Online]. Available: http://www-device.eecs.berkeley.edu/~ptm
12. R. K. Krishnamurthy, A. Alvandpour, G. Balamurugan, N. R. Shanbhag, K. Soumyanath, and S. Y. Borkar, "A 130-nm 6-GHz 256 × 32 bit leakage-tolerant register file," IEEE J. Solid-State Circuits, vol. 37, pp. 624-632, May 2002.