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Volumn , Issue , 2004, Pages 537-540

A vectorless estimation of Maximum Instantaneous Current for sequential circuits

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; COMBINATORIAL CIRCUITS; ELECTRIC CURRENTS; ELECTRIC POWER SYSTEMS; ESTIMATION; INFORMATION ANALYSIS; SIGNAL PROCESSING; SWITCHING; VECTORS;

EID: 16244387662     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (13)

References (16)
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  • 2
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    • Estimation of maximum switching activity in digital VLSI circuits
    • Sacramento, CA, August 3-6
    • S. Bobba and I. N. Hajj, "Estimation of maximum switching activity in digital VLSI circuits," in Proc. of Midwest Symp. On Circuits and Syst., Sacramento, pp. 1130-1133, CA, August 3-6, 1997.
    • (1997) Proc. of Midwest Symp. on Circuits and Syst. , pp. 1130-1133
    • Bobba, S.1    Hajj, I.N.2
  • 3
    • 0025439702 scopus 로고
    • Estimation of maximum current in MOS IC logic circuits
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    • (1990) IEEE Trans. on CAD , pp. 642-654
    • Chowdhury, S.1    Barkatullah, J.S.2
  • 5
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    • Estimation of power dissipation in CMOS combinational circuits using boolean function manipulation
    • March
    • S. Devadas, K. Keutzer, and J. White, "Estimation of power dissipation in CMOS combinational circuits using Boolean function manipulation," IEEE Trans. on CAD, pp. 373-383, March 1992.
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  • 8
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    • Jiang, Y.M.1    Krstic, A.2    Cheng, K.T.3
  • 9
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    • Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution
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    • H. Kriplani, F. Najm, and I. N. Hajj, "Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: algorithms, signal correlations, and their resolution," IEEE Trans. on CAD, pp. 998-1012, August 1995.
    • (1995) IEEE Trans. on CAD , pp. 998-1012
    • Kriplani, H.1    Najm, F.2    Hajj, I.N.3
  • 10
    • 0029723904 scopus 로고    scopus 로고
    • PECS: A peak current and power simulator for CMOS combinational circuits
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  • 11
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    • Murayama, T.1    Ogawa, K.2    Yamaguchi, H.3
  • 12
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  • 13
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  • 14
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  • 15
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  • 16
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.