Maximization of power dissipation in large CMOS circuits considering spurious transitions

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

Volumn 47, Issue 4, 2000, Pages 483-490

  Wang, Chuan Yu ^a   Roy, Kaushik ^b  

^a SYNOPSYS INC   (United States)

^b PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; ELECTRIC POWER SUPPLIES TO APPARATUS; ESTIMATION; LOGIC GATES; MONTE CARLO METHODS; OPTIMIZATION; RESPONSE TIME (COMPUTER SYSTEMS); SEQUENTIAL CIRCUITS; VLSI CIRCUITS;

AUTOMATIC TEST GENERATION; POWER DEMAND; POWER DISSIPATION; STATIC TIMING ANALYSIS;

CMOS INTEGRATED CIRCUITS;

EID: 0033740322     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/81.841850     Document Type: Article

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