Worst case tolerance analysis of linear analog circuits using sensitivity bands

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

Volumn 47, Issue 8, 2000, Pages 1138-1145

  Tian, Michael W ^a   Richard Shi, C J ^b  

^a CADENCE DESIGN SYSTEMS   (United States)

^b University of Washington   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BRIDGE CIRCUITS; COMPUTATIONAL METHODS; COMPUTER SIMULATION; LINEAR EQUATIONS; LINEAR NETWORKS; MONTE CARLO METHODS; PARAMETER ESTIMATION; SENSITIVITY ANALYSIS; THEOREM PROVING;

INTERVAL ANALYSIS; LINEAR ANALOG CIRCUITS; SENSITIVITY BAND COMPUTATION; VERTEX ANALYSIS; WORST CASE TOLERANCE ANALYSIS;

LINEAR NETWORK SYNTHESIS;

EID: 0034242052     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/81.873869     Document Type: Article

References (14)

1. G. Alefeld, Introduction to Interval Computations. New York: Academic, 1983.
2. K. J. Antreich, H. E. Graeb, and C. U. Wieser, "Circuit analysis and optimization driven by worst-case distances," IEEE Trans. ComputerAided Design, vol. 13, pp. 57-71, Jan. 1994.
3. J. W. Bandler, P. C. Liu, and J. H. K. Chen, "Worst-case network tolerance optimization," IEEE Trans. Microwave Theory Tech., vol. 23, pp. 630-641, Aug. 1975.
4. R. K. Brayton, A. J. Huffman, and T. R. Scott, "A theorem on inverse of convex sets of real matrices with application to the worst case DC problem," IEEE Trans. Circuits Syst., vol. 24, pp. 409-4115, Aug. 1977.
5. A. Dharchoudhury and S. M. Kang, "Worst-case analysis and optimization of VLSI circuit performances," IEEE Trans. Computer-Aided Design, vol. 14, pp. 481-492, Apr. 1995.
6. N. Femia and G. Spagnuolo, "Genetic optimization of interval arithmetic-based worst case circuit tolerance analysis," IEEE Trans. Circuits Syst. I, vol. 46, pp. 1441-1456, Dec. 1999.
7. L. P. Huang and R. E. Bryant, "Intractability in linear switch-level simulation," IEEE Trans. Computer-Aided Design, vol. 12, pp. 829-836, June 1993.
8. A. Levkorich, E. Zeheb, and N. Cohen, "Frequency response envelopes of a family of uncertain continuous-time systems," IEEE Trans. Circuits Syst. I, vol. 42, pp. 156-165, Mar. 1995.
9. A. Pahwa and R. A. Rohrer, "Band-faults: Efficient approximations to fault bands for the simulation before fault diagnosis of linear circuits," IEEE Trans. Circuits Syst., vol. 29, pp. 81-88, Feb. 1982.
10. C. J. R. Shi and M. W. Tian, "Simulation and sensitivity of linear analog circuits under parameter variations," ACM Trans. Design Automat. Electron. Syst., vol. 4, pp. 280-312, July 1999.
11. I. M. Sobol, A Primer for the Monte Carlo Method. Boca Raton, FL: CRC, 1994.
12. R. Spence and R. S. Soin, Tolerance Design of Electronic Circuits. Reading, PA: Addison-Wesley, 1988.
13. M. W. Tian and C. J. R. Shi, "Worst-case analysis of linear analog circuits using sensitivity bands," in Proc. IEEE Int. Symp. Circuits Syst., 1998, pp. 110-113.
14. W. Tian, X. T. Ling, and R. W. Liu, "Novel methods for circuit worst-case tolerance analysis," IEEE Trans. Circuits Syst. I, vol. 43, pp. 272-278, Apr. 1996.