Dynamic zero-sensitivity scheme for low-power cache memories

IEEE Micro

Volumn 25, Issue 4, 2005, Pages 20-32

  Chang, Yen Jen ^a   Lai, Feipei ^b  

^a NATIONAL CHUNG HSING UNIVERSITY   (Taiwan)

^b NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; ELECTRIC POWER SUPPLIES TO APPARATUS; LOGIC CIRCUITS; LOGIC DESIGN; MICROPROCESSOR CHIPS; RANDOM ACCESS STORAGE; SYSTEMS ANALYSIS;

BITLINES; CACHE POWER CONSUMPTION; DYNAMIC ZERO-SENSITIVITY; PORTABLE INSTRUCTION SET ARCHITECTURE (PISA); POWER REDUCTION;

CACHE MEMORY;

EID: 25844484595     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2005.64     Document Type: Article

References (12)

1. J. F. Edmondson et al., "Internal Organization of the Alpha 21164, a 300-MHz 64-Bit Quad-Issue CMOS RISC Microprocessor," Digital Technical J., vol. 7, no. 1, 1995, pp. 119-135.
2. J. Montanaro et al., "A 160 MHz, 32b 0.5W CMOS RISC Microprocessor," Proc. 43rd IEEE Int'l Solid-State Circuits Conf. (ISSCC 96), IEEE Press. 1996, pp. 214-215, 447.
3. C. Lee, M. Potkonjak and W.H. Mangione-Smith, "MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems," Proc. 30th Int'l Symp. Microarchitecture (Micro 30), IEEE Press, 1997, pp. 330-335.
4. B. Amrutur and M. Horowitz, "Techniques to Reduce Power in Fast Wide Memories (CMOS SRAMs)," Proc. IEEE Symp. Low Power Electronics, IEEE Press, 1994, pp. 92-93.
5. D.C. Burger and T.M. Austin, "The SimpleScalar Tool Set, Version 2.0," Computer Architecture News, vol. 25, no. 3, June 1997, pp. 13-25,
6. J.L. Hennessy and D. A. Patterson Computer Architecture: A Quantitative Approach, 2nd ed., Morgan Kaufmann, 1995.
7. N. Azizi et al., Asymmetric-Cell Caches: Exploiting Bit Value Biases to Reduce Leakage Power in Deep-Submicron, High-Performance Caches, tech report TR-01-01-02, ECE Computer Group, Univ. of Toronto, 2002.
8. J.H. Tseng and K. Asanovic, "Energy-Efficient Register Access," Proc. 13th Symp. Integrated Circuits and Systems Design, IEEE Press, 2000, pp. 377-382.
9. B.K. Park, Y.S. Chang, and C.M. Kyung, "Confirming Inverted Data Store for Low Power Memory," Proc. Int'l Symp. Low Power Electronics and Design (ISLPED 99), IEEE Press, 1999, pp. 91-93.
10. P. Shivakumar and N.P. Jouppi, CACTI 3.0: An Integrated Cache Timing, Power, and Area Model, Compaq WRL research report, 2001/2.
11. M. Ukita et al., "A Single-Bit-Line Cross-Point Cell Activation (SCPA) Architecture for Ultra-Low-Power SRAM's," IEEE J. Solid-State Circuits, vol. 28, no. 11, Nov. 1993, pp. 1114-1118.
12. K. Inoue, T. Ishihara, and K. Murakami, "Way-Predicting Set-Associative Cache for High Performance and Low Energy Consumption," Proc. Int'l Symp. Low Power Electronics and Design (ISLRED 99), IEEE Press, 1999, pp. 273-275.