Experimental verification of row-by-row variable VDD scheme reducing 95% active leakage power of SRAM's

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn 2005, Issue , 2005, Pages 162-165

  Saliba, Fayez Robert ^a   Kawaguchi, Hiroshi ^b   Sakurai, Takayasu ^a  

^a UNIVERSITY OF TOKYO   (Japan)

^b INSTITUTE OF INDUSTRIAL SCIENCE   (Japan)

Author keywords

Low active leakage; Low power; Self alignment row by row variable V DD; SRAM

Indexed keywords

ELECTRIC POWER SYSTEMS; LEAKAGE CURRENTS; TIMING CIRCUITS; VLSI CIRCUITS;

LOW ACTIVE LEAKAGE; LOW POWER; SELF-ALIGNMENT ROW-BY-ROW VARIABLE V DD;

STATIC RANDOM ACCESS STORAGE;

EID: 28044461811     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2005.1469356     Document Type: Conference Paper

References (3)

1. A. Agarwal, H. Li, and K. Roy, "A Single Vt Low-Leakage Gated-Ground Cache for Deep Submicron," JSSC, pp. 319-328, Feb. 2003.
2. K. Osada, Y. Saitoh, E. Ibe, and K. Ishibashi, "16.7fA/Cell Tunnel-Leakage-Suppressed 16 Mb SRAM for Handling Cosmic-Ray-Induced Multi-Errors," ISSCC, pp. 302-303, Feb. 2003.
3. DD SRAM's," ISLPED, pp. 66-71, Aug. 2003.