A 21-GHz 8-modulus prescaler and a 20-GHz phase-locked loop fabricated in 130-nm CMOS

IEEE Journal of Solid-State Circuits

Volumn 42, Issue 6, 2007, Pages 1240-1249

  Ding, Yanping ^a,b   Kenneth, K O ^a,b  

^a IEEE   (United States)

^b UNIVERSITY OF FLORIDA   (United States)

Author keywords

CMOS; Dual modulus prescaler; Integer N phase locked loop (PLL); Low power; Multimodulus prescaler

Indexed keywords

CURRENT MODE LOGIC (CML); DUAL-MODULUS PRESCALER; INTEGER-N PHASE-LOCKED LOOP (PLL); MULTIMODULUS PRESCALERS;

ELECTRIC CURRENTS; FLIP CHIP DEVICES; PHASE LOCKED LOOPS; PHASE NOISE; POWER SUPPLY CIRCUITS; SYNCHRONOUS MACHINERY;

CMOS INTEGRATED CIRCUITS;

EID: 34249853686     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2007.897140     Document Type: Article

References (27)

1. Y. Su, J.-J. Lin, and K. K. O, "A 20-GHz CMOS RF down-conversion with an on-chip antenna," IEEE ISSCC Dig. Tech. Papers, pp. 270-271, Feb. 2005.
2. H. Hashemi, X. Guan, A. Komijani, and A. Hajimiri, "A 24-GHz SiGe phased-array receiver - LO phase-shifting approach," IEEE Trans. Miaow. Theory Tech., vol. 53, no. 2, pp. 614-626, Feb. 2005.
3. A. Natarajan, A. Komijani, and A. Hajimiri, "A 24 GHz phased-array transmitter in 0.18 μm CMOS," IEEE ISSCC Dig. Tech. Papers, pp. 212-213, Feb. 2005.
4. K.-W. Yu, Y.-L. Lu, D.-C. Chang, V. Liang, and M. F. Chang, "K-band low-noise amplifiers using 0.18 μm CMOS technology." IEEE Microw. Wireless Compon. Lett., vol. 14, no. 3, pp. 106-108, Mar. 2004.
5. A. W. L. Ng, G. C. T. Leung, K.-C. Kwok, L. L. K. Leung, and H. C. Luong, "A 1-V 24-GHz 17.5-mW phase-locked loop in a 0.18 μm CMOS process," IEEE J. Solid-State Circuits, vol. 41, no. 6, pp. 1236-1244, Jun. 2006.
6. J. Kim, J. K. Kim, B. J. Lee, N. Kim, D. K. Jeong, and W. Kim, "A 20-GHz phase-locked loop for 40-Gb/s serializing transmitter in 0.13-um CMOS," IEEE J. Solid-State Circuits, vol. 41, no. 4, pp. 899-908, Apr. 2006.
7. M. Tiebout, C. Sandner, H.-D. Wohlmuth, N. D. Dalt, and E. Thaller, "A fully integrated 13 GHz ΔΣ fractional-N PLL in 0.13 μm CMOS," in IEEE ISSCC Dig. Tech. Papers, 2004. pp. 386-387.
8. D.-J. Yang and K. K. O, "A 14-GHz 256/257 dual-modulus prescaler with secondary feedback and its application to a monolithic CMOS 10.4-GHz phase-locked loop," IEEE Trans. Microw. Theory Tech., vol. 52, no. 2, pp. 461-468, Feb. 2004.
9. M. Zargari, "A 5-GHz CMOS transceiver for IEEE 802.11a wireless LAN systems," IEEE J. Solid State Circuits, vol. 37, no. 12, pp. 1688-1694, Dec. 2002.
10. H.-D. Wohlmuth and D. Kehrer, "A 15 GHz 256/257 dual-modulus prescaler in 120 nm CMOS," in Proc. Eur. Solid-State Circuits Conf., Sep. 2003, pp. 77-80.
11. H.-D. Wohlmuth and D. Kehrer, "A 17 GHz dual-modulus prescaler in 120 nm CMOS," in IEEE RFIC Symp. Dig. Papers, Jun. 2003, pp. 479-482.
12. Y. Yamauchi, O. Nakajima, K. Nagata, and M. Hirayama, "A 15-GHz monolithic two-modulus prescaler," IEEE J. Solid-State Circuits, vol. 26, no. 11, pp. 1632-11636, Nov. 1991.
13. C.-M. Hung, B. A. Floyd, N. Park, and K. K. O, "Fully integrated 5.35-GHz CMOS VCOs and prescalers," IEEE Trans. Microw. Theory Tech., vol. 49, no. 1, pp. 17-22, Jan. 2001.
14. C. Cao and K. K. O, "A power efficient 26-GHz 32:1 static frequency divider in 130-nm bulk CMOS," IEEE Miaow. Wireless Compon. Lett., vol. 15, no. 11, pp. 721-723, Nov. 2005.
15. Y. Ding and K. K. O, "A low-power 17-GHz 256/257 dual-modulus prescaler fabricated in a 130-nm CMOS process," in IEEE RFIC Symp. Dig. Papers, Jun. 2005, pp. 465-468.
16. C. M. Hung, N. Barton, M. Lee, and D. Leipold, "An ultta low phase noise GSM local Oscillator in a 0.09-μm standard digital CMOS process with No high-Q inductors," in IEEE RFIC Symp. Dig. Papers, Jun. 2004, pp. 483-486.
17. K. K. O, "Estimation methods for quality factors of inductors fabricated in silicon integrated circuit process technologies," IEEE J. Solid-State Circuits, vol. 13, no. 8, pp. 1249-1252, Aug. 1998.
18. C. P. Yue and S. S. Wong, "On-chip spiral inductors with patterned ground shields for Si-based RF IC's," IEEE J. Solid-State Circuits, vol. 33, no. 6, pp. 743-752, Jun. 1998.
19. S.-M. Yim and K. K. O, "The effects of a ground shield on the characteristics and performance of spiral inductors," IEEE J. Solid-State Circuits, vol. 37, no. 2, pp. 237-244, Feb. 2002.
20. S. R. Whiteley, FastHenry Version 3.0wr. Feb. 2001 [Online], Available: http://www.sr-ware.com
21. D. Mijuskovic, M. Bayer, T. Chomicz, N. Garg, F. James, P. McEntarfer, and J. Porter, "Cell-based fully integrated CMOS frequency synthesizers," IEEE J. Solid-State Circuits, vol. 29, no. 3, pp. 271-279, Mar. 1994.
22. C.-M. Hung, Y.-C. Ho, I.-C. Wu, and K. K. O, "High-Q capacitors implemented in a CMOS process for low-power wireless applications," IEEE Trans. Microw. Theory Tech., vol. 46, no. 5, pp. 505-511, May 1998.
23. T. Soorapanth, C. P. Yue, D. K. Shaeffer, T. I. Lee, T. I., and S. S. Wong, "Analysis and optimization of accumulation-mode varactor for RF ICs," in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 1998, pp. 32-33.
24. C. M. Hung, Y. C. Ho, I. C. Wu, and K. K. O, "High-Q capacitors implemented in a CMOS process for low-power wireless application," IEEE Trans. Microw. Theory Tech., vol. 46, no. 5, pp. 505-511, May 1998.
25. S.-M. Yim and K. K. O, "Demonstration of a switched resonator concept in a dual-band monolithic CMOS LC-Tuned VCO," in Proc. Custom Integrated Circuits Conf, San Diego, CA, May 2001, pp. 205-208.
26. J.-M. Mourant, J. Imbornonr, and T. Tewksbury, "A low phase noise monolithic VCO in SiGe BiCMOS," in Proc. IEEE Radio Frequency Integr. Circuits Symp., Boston, MA, Jun. 2000, pp. 65-68.
27. Z. Li and K. K. O, "A 900-MHz 1.5-V CMOS voltage-controlled oscillator using switched resonators with a wide tuning range," IEEE Microw. Wireless Compon. Lett., vol. 13, no. 4, pp. 137-139, Apr. 2003.