A 1-V 24-GHz 17.5-mW phase-locked loop in a 0.18-μm CMOS process

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 6, 2006, Pages 1236-1243

  Ng, Alan W L ^b   Leung, Gerry C T ^c   Kwok, Ka Chun ^d   Leung, Lincoln L K ^b   Luong, Howard C ^a,b  

^a IEEE   (Hong Kong)

^b HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

^c Science Park ^*  (Hong Kong)

^d DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

Clock generation; Low power; Low voltage; Oseillator; Phase locked loop (PLL); Receiver; Synthesizer; Transceiver; Transformer; Voltage controlled oscillator (VCO)

Indexed keywords

CLOCK GENERATION; LOW POWER; LOW VOLTAGE; OSEILLATOR; RECEIVERS; SYNTHESIZERS; TRANSFORMERS;

ELECTRIC TRANSFORMERS; PHASE LOCKED LOOPS; SPURIOUS SIGNAL NOISE; TRANSCEIVERS; VARIABLE FREQUENCY OSCILLATORS;

CMOS INTEGRATED CIRCUITS;

EID: 33746638092     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.874332     Document Type: Article

References (11)

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