Analysis and optimization of accumulation-mode varactor for RF

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 1998, Pages 32-33

  Soorapanth, Theerachet ^a   Yue, C Patrick ^a   Shaeffer, Derek K ^a   Lee, Thomas H ^a   Wong, S Simon ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; SEMICONDUCTOR DEVICE TESTING; TUNING;

QUALITY FACTORS;

VARACTORS;

EID: 0031639119     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)