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Volumn 41, Issue 4, 2006, Pages 899-907

A 20-GHz phase-locked loop for 40-Gb/s serializing transmitter in 0.13-μm CMOS

Author keywords

CMOS; Frequency divider; Phase locked loop (PLL); Pulsed latch; Reference spur; VCO optimization

Indexed keywords

FREQUENCY DIVIDER; PULSED LATCH; REFERENCE SPUR; VCO OPTIMIZATION;

EID: 33645663478     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.870766     Document Type: Conference Paper
Times cited : (45)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.