-
1
-
-
28144448848
-
Circuit techniques for a 40 Gb/s transmitter in 0.13-μm CMOS
-
Feb.
-
J. Kim et al., "Circuit techniques for a 40 Gb/s transmitter in 0.13-μm CMOS," in IEEE ISSCC Dig. Tech. Papers, Feb. 2005, pp. 150-151.
-
(2005)
IEEE ISSCC Dig. Tech. Papers
, pp. 150-151
-
-
Kim, J.1
-
2
-
-
33645687517
-
A 20-GHz phase-locked loop for 40 Gb/s serializing transmitter in 0.13-μm CMOS
-
Jun.
-
_, "A 20-GHz phase-locked loop for 40 Gb/s serializing transmitter in 0.13-μm CMOS," in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2005, pp. 144-147.
-
(2005)
Symp. VLSI Circuits Dig. Tech. Papers
, pp. 144-147
-
-
-
3
-
-
0345293104
-
Design of CMOS adaptive bandwidth PLL/DLLs: A general approach
-
Nov.
-
_, "Design of CMOS adaptive bandwidth PLL/DLLs: a general approach." IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 50, no. 11, pp. 860-869, Nov. 2003.
-
(2003)
IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process.
, vol.50
, Issue.11
, pp. 860-869
-
-
-
4
-
-
0038380469
-
A stabilization technique for phase-locked frequency synthesizers
-
Jun.
-
T. C. Lee and B. Razavi, "A stabilization technique for phase-locked frequency synthesizers." IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 888-894, Jun. 2003.
-
(2003)
IEEE J. Solid-state Circuits
, vol.38
, Issue.6
, pp. 888-894
-
-
Lee, T.C.1
Razavi, B.2
-
5
-
-
0035506811
-
A low-jitter 125-1250-MHz process-independent and ripple-poleless 0.18-μm CMOS PLL based on a sample-reset loop filter
-
Nov.
-
A. Maxim et al., "A low-jitter 125-1250-MHz process-independent and ripple-poleless 0.18-μm CMOS PLL based on a sample-reset loop filter," IEEE J. Solid-State Circuits, vol. 36, no. 11, pp. 1673-1683, Nov. 2001.
-
(2001)
IEEE J. Solid-state Circuits
, vol.36
, Issue.11
, pp. 1673-1683
-
-
Maxim, A.1
-
6
-
-
0242551728
-
Self-biased, high-bandwidth, low-jitter 1-to-4096 multiplier clock-generator PLL
-
Nov.
-
J. G. Maneatis et al., "Self-biased, high-bandwidth, low-jitter 1-to-4096 multiplier clock-generator PLL," IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 1795-1803, Nov. 2003.
-
(2003)
IEEE J. Solid-state Circuits
, vol.38
, Issue.11
, pp. 1795-1803
-
-
Maneatis, J.G.1
-
7
-
-
0036053142
-
Fast and accurate behavioral simulation of fractional-N synthesizers and other PLL/DLL circuits
-
Jun.
-
M. H. Perrott, "Fast and accurate behavioral simulation of fractional-N synthesizers and other PLL/DLL circuits," in Proc. Design Automation Conf., Jun. 2002, pp. 498-503.
-
(2002)
Proc. Design Automation Conf.
, pp. 498-503
-
-
Perrott, M.H.1
-
9
-
-
2442658215
-
Design of CMOS for 60 GHz applications
-
Feb.
-
C. H. Doan et al., "Design of CMOS for 60 GHz applications," in IEEE ISSCC Dig. Tech. Papers, Feb. 2004, pp. 440-441.
-
(2004)
IEEE ISSCC Dig. Tech. Papers
, pp. 440-441
-
-
Doan, C.H.1
-
10
-
-
4544346271
-
Standing wave oscillators utilizing wave-adaptive tapered transmission lines
-
Jun.
-
W. Andress and D. Ham, "Standing wave oscillators utilizing wave-adaptive tapered transmission lines," in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2004, pp. 50-53.
-
(2004)
Symp. VLSI Circuits Dig. Tech. Papers
, pp. 50-53
-
-
Andress, W.1
Ham, D.2
-
11
-
-
0037818279
-
Performance optimized microstrip coupled VCOs for 40-GHz and 43-GHz OC-768 optical transmission
-
Jul.
-
D. K. Shaeffer and S. Kudszus, "Performance optimized microstrip coupled VCOs for 40-GHz and 43-GHz OC-768 optical transmission," IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1130-1138, Jul. 2003.
-
(2003)
IEEE J. Solid-state Circuits
, vol.38
, Issue.7
, pp. 1130-1138
-
-
Shaeffer, D.K.1
Kudszus, S.2
-
12
-
-
0035369538
-
Concepts and methods in optimization of integrated LC VCOs
-
Jun.
-
D. Ham and A. Hajimiri, "Concepts and methods in optimization of integrated LC VCOs," IEEE J. Solid-State Circuits, vol. 36, no. 6, pp. 896-909, Jun. 2001.
-
(2001)
IEEE J. Solid-state Circuits
, vol.36
, Issue.6
, pp. 896-909
-
-
Ham, D.1
Hajimiri, A.2
-
14
-
-
0035507075
-
Rotary traveling-wave oscillator arrays: A new clock technology
-
Nov.
-
J. Wood et al., "Rotary traveling-wave oscillator arrays: a new clock technology," IEEE J. Solid-State Circuits, vol. 36, no. 11, pp. 1654-1665, Nov. 2001.
-
(2001)
IEEE J. Solid-state Circuits
, vol.36
, Issue.11
, pp. 1654-1665
-
-
Wood, J.1
-
15
-
-
0037630670
-
10 GHz clock distribution using coupled standing-wave oscillators
-
Feb.
-
F. O'Mahony et al., "10 GHz clock distribution using coupled standing-wave oscillators," in IEEE ISSCC Dig. Tech. Papers, Feb. 2003, pp. 428-429.
-
(2003)
IEEE ISSCC Dig. Tech. Papers
, pp. 428-429
-
-
O'Mahony, F.1
-
17
-
-
0022795057
-
Clock schemes for high-speed digital systems
-
Oct.
-
S. Unger and C. Tan, "Clock schemes for high-speed digital systems," IEEE Trans. Comput., vol. 35, no. 10, pp. 880-895, Oct. 1986.
-
(1986)
IEEE Trans. Comput.
, vol.35
, Issue.10
, pp. 880-895
-
-
Unger, S.1
Tan, C.2
-
18
-
-
0001612587
-
Fractional-frequency generators utilizing regenerative modulation
-
Jul.
-
R. L. Miller, "Fractional-frequency generators utilizing regenerative modulation," in Proc. Inst. Radio Eng., Jul. 1939, vol. 27, pp. 446-456.
-
(1939)
Proc. Inst. Radio Eng.
, vol.27
, pp. 446-456
-
-
Miller, R.L.1
-
19
-
-
0032652401
-
Superharmonic injection-locked frequency dividers
-
Jun.
-
H. R. Rategh and T. H. Lee, "Superharmonic injection-locked frequency dividers," IEEE J. Solid-State Circuits, vol. 34, no. 6, pp. 813-821, Jun. 1999.
-
(1999)
IEEE J. Solid-state Circuits
, vol.34
, Issue.6
, pp. 813-821
-
-
Rategh, H.R.1
Lee, T.H.2
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