A 20-GHz phase-locked loop for 40-Gb/s serializing transmitter in 0.13-μm CMOS

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 4, 2006, Pages 899-907

  Kim, Jaeha ^a,b,c   Kim, Jeong Kyoum ^a,b   Lee, Bong Joon ^a,b,c   Kim, Namhoon ^a,b,d   Jeong, Deog Kyoon ^a,b   Kim, Wonchan ^a,b  

^a IEEE   (South Korea)

^b Seoul National University   (South Korea)

^c Seoul National University   (South Korea)

^d Silicon Image Inc   (United States)

Author keywords

CMOS; Frequency divider; Phase locked loop (PLL); Pulsed latch; Reference spur; VCO optimization

Indexed keywords

FREQUENCY DIVIDER; PULSED LATCH; REFERENCE SPUR; VCO OPTIMIZATION;

CMOS INTEGRATED CIRCUITS; JITTER; MICROSTRIP DEVICES; OPTIMIZATION; TRANSMITTERS; VARIABLE FREQUENCY OSCILLATORS;

PHASE LOCKED LOOPS;

EID: 33645663478     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.870766     Document Type: Conference Paper

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