Design and test of a scalable security processor

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 1, Issue , 2005, Pages 372-375

  Su, Chih Pin ^a   Wang, Chen Hsing ^a   Cheng, Kuo Liang ^a   Huang, Chih Tsun ^a   Wu, Cheng Wen ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; CRYPTOGRAPHY; DESIGN FOR TESTABILITY; INTEGRATED CIRCUIT DESIGN; RANDOM NUMBER GENERATION;

CMOS TECHNOLOGY; CRYPTOGRAPHIC FUNCTIONS; DESIGN AND TESTS; NUMBER OF DATUM; PROGRAMMING MODELS; SCALABLE SECURITIES; SECURITY APPLICATION; SECURITY PROCESSOR;

HARDWARE SECURITY;

EID: 51849110669     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1120725.1120872     Document Type: Conference Paper

References (6)

1. C.-P. Su, T.-F. Lin, C.-T. Huang, and C.-W. Wu. "A high-throughput low-cost AES processor". IEEE Communications Magazine. vol. 41. no. 12, pp. 86-91, Dec. 2003.
2. C.-H Wang, C.-P Su, C.-T Huang, and C.-W. Wu, "A word-based rsa crypto-processor with enhanced pipeline performance", in Proc. 4th IEEE Asia-Pacific Conf. ASIC. Fukuoka, Japan, Aug. 2004 (to appear).
3. M.-Y. Wang, C-P. Su, C.-T. Huang. and C.-W. Wu, "An HMAC processor with integrated SHA-I and MD5 algorithms", in Proc. Asia and South Pacific Design Automation Conf. (ASP-DAC), Yokohama, Jan. 2004, pp. 454-458.
4. ARM Components, Inc., AMBA Specification Rev2.0, May 1999.
5. National Institute of Standards and Technology (NIST), Security Requirements for Cryptographic Modules, National Technical Information Service, Springfield, VA 22161, May 2001.
6. C.-W. Wang, J.-R. Huang, K.-L. Cheng, H.-S. Hsu, C.-T. Huang, C.-W. Wu. and Y.-L. Lin, "A test access control and test integration system for system-on-chip". in Sixth IEEE Int. Workshop on Testing Embedded Core-Based System-Chips (TECS), Monterey, California, May 2002, pp. P2.1-P2.8.