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Volumn 28, Issue 5, 2007, Pages 376-378

Impacts of notched-gate structure on contact etch stop layer (CESL) stressed 90-nm nMOSFET

Author keywords

Contact etch stop layer (CESL) stresses; Mobility enhancement; Notched gate; Stress engineering

Indexed keywords

COMPUTER AIDED ANALYSIS; ETCHING; GATE DIELECTRICS; TENSILE STRESS;

EID: 34247595525     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2007.895425     Document Type: Article
Times cited : (23)

References (15)
  • 1
    • 0033697180 scopus 로고    scopus 로고
    • Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors
    • T. Ghani, K. Mistry, P. Packan, S. Thompson, M. Stealer, S. Tyagi, and M. Bohr, "Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors," in VLSI Symp. Tech. Dig., 2000, pp. 174-175.
    • (2000) VLSI Symp. Tech. Dig , pp. 174-175
    • Ghani, T.1    Mistry, K.2    Packan, P.3    Thompson, S.4    Stealer, M.5    Tyagi, S.6    Bohr, M.7
  • 12
  • 15
    • 0027592983 scopus 로고
    • 1/f noise in hot-carrier damaged MOSFET's: Effects of oxide charge and interface traps
    • May
    • M. H. Tsai and T. P. Ma, "1/f noise in hot-carrier damaged MOSFET's: Effects of oxide charge and interface traps," IEEE Electron Device Lett., vol. 14, no. 5, pp. 256-258, May 1993.
    • (1993) IEEE Electron Device Lett , vol.14 , Issue.5 , pp. 256-258
    • Tsai, M.H.1    Ma, T.P.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.