Experimental and simulation study on sub-50 nm CMOS design

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue TECHNOLOGY SYMP., 2001, Pages 35-36

  Pidin, S ^a   Shido, H ^a   Yamamoto, T ^a   Horiguchi, N ^a   Kurata, H ^a   Sugii, T ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; GATES (TRANSISTOR); ION IMPLANTATION; POLYSILICON; THRESHOLD VOLTAGE;

DRAIN CURRENT;

CMOS INTEGRATED CIRCUITS;

EID: 0034789115     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)