Single stress liner for both NMOS and PMOS current enhancement by a novel ultimate spacer process

Technical Digest - International Electron Devices Meeting, IEDM

Volumn 2005, Issue , 2005, Pages 836-839

  Liu, Y C ^a   Pan, J W ^a   Chang, T Y ^a   Liu, P W ^a   Lan, B C ^a   Tung, C H ^a   Tsai, C H ^a   Chen, T F ^a   Lee, C J ^a   Wang, W M ^a   Chen, Y A ^a   Shih, H L ^a   Tung, L Y ^a   Cheng, L W ^a   Shen, T M ^a   Chiang, S C ^a   Lu, M F ^a   Chang, W T ^a   Luo, Y H ^b   Nayak, D ^b   Gitlin, D ^b   Meng, H L ^a   Tsai, C T ^a   more..

^a UNITED MICROELECTRONICS CORPORATION   (Taiwan)

^b XILINX INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

PRODUCT QUALIFICATION; STRAIN ENHANCEMENT; STRESS LINER; ULTIMATE SPACER PROCESS (USP);

CMOS INTEGRATED CIRCUITS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); NANOTECHNOLOGY; SEMICONDUCTOR DEVICE MANUFACTURE;

MOS DEVICES;

EID: 33847694288     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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