The potential of the cell processor for scientific computing

Proceedings of the 3rd Conference on Computing Frontiers 2006, CF '06

Volumn 2006, Issue , 2006, Pages 9-20

  Williams, Samuel ^a   Shalf, John ^a   Oliker, Leonid ^a   Kamil, Shoaib ^a   Husbands, Parry ^a   Yelick, Katherine ^a  

^a LAWRENCE BERKELEY NATIONAL LABORATORY   (United States)

Author keywords

Cell processor; FFT; GEMM; Sparse matrix; SpMV; Stencil; Three level memory

Indexed keywords

PROGRAMMING CELLS; SCIENTIFIC COMPUTATION; SPARSE MATRIX; THREE LEVEL MEMORY;

COMPUTER AIDED DESIGN; COMPUTER SIMULATION; FAST FOURIER TRANSFORMS; MICROPROCESSOR CHIPS; NATURAL SCIENCES COMPUTING;

DATA STORAGE EQUIPMENT;

EID: 34247349114     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1128022.1128027     Document Type: Conference Paper

References (32)

1. G. Blelloch, M. Heroux, and M. Zagha. Segmented operations for sparse matrix computation on vector multiprocessors. Technical Report CMU-CS-93-173, CMU, 1993.
2. Cactus homepage. http://www.cactuscode.org.
3. L. Cannon. A Cellular Computer to Implement the Kalman Filter Algorithm. PhD thesis, Montana State University, 1969.
4. Cell broadband engine architecture and its first implementation, http://www-128.ibm.com/developerworks/power/library/pa-cellperf/.
5. Chombo homepage. http://seesar.Ibl.gov/anag/chombo.
6. E. D'Azevedo, M. R. Fahey, and R. T. Mills. Vectorized sparse matrix multiply for compressed row storage format. In International Conference on Computational Science (ICCS), pages 99-106, 2005.
7. FFTW speed tests. http://www.fftw.org.
8. B. Flachs, S. Asano, S. Dhong, et al. A streaming processor unit for a cell processor. ISSCC Dig. Tech. Papers, pages 134-135, February 2005.
9. P. Francesco, P. Marchal, D. Atienzaothers, et al. An integrated hardware/software approach for run-time scratchpad management. In Proceedings of the 41st Design Automation Conference, June 2004.
10. Ibm cell specifications. http://www.research.ibm.com/cell/home.html.
11. E.-J. Im, K. Yelick, and R. Vuduc. Sparsity: Optimization framework for sparse matrix kernels. International Journal of High Performance Computing Applications, 2004.
12. The Berkeley Intelligent RAM (IRAM) Project. http://iram.cs.berkeley.edu.
13. G. Jin, J. Mellor-Crummey, and R. Fowlerothers. Increasing temporal locality with skewing and recursive blocking. In Proc. SC2001, 2001.
14. J. Kahle, M. Day, H. Hofstee, et al. Introduction to the cell multiprocessor. IBM Journal of R&D, 49(4), 2005.
15. S. Kamil, P. Husbands, L. Oliker, et al. Impact of modern memory subsystems on cache optimizations for stencil computations. In ACM Workshop on Memory System Performance, June 2005.
16. M. Kandemir, J. Ramanujam, M. Irwin, et al. Dynamic management of scratch-pad memory space. In Proceedings of the Design Automation Conference, June 2001.
17. P. Keltcher, S. Richardson, S. Siu, et al. An equal area comparison of embedded dram and sram memory architectures for a chip multiprocessor. Technical report, HP Laboratories, April 2000.
18. B. Khailany, W. Dally, S. Rixner, et al. Imagine: Media processing with streams. IEEE Micro, 21(2), March-April 2001.
19. M. Kondo, H. Okawara, H. Nakamura, et al. Scima: A novel processor architecture for high performance comp uting. In 4th International Conference on High Performance Computing in the Asia Pacific Region, volume 1, May 2000.
20. A. Kunimatsu, N. Ide, T. Sato, et al. Vector unit architecture for emotion synthesis. IEEE Micro, 20(2), March 2000.
21. Z. Li and Y. Song. Automatic tiling of iterative stencil loops. ACM Transactions on Programming Language Systems, 26(6), 2004.
22. S. Mueller, C. Jacobi, C. Hwa-Joon, et al. The vector floating-point unit in a synergistic processor element of a cell processor. In 17th IEEE Annual Symposium on Computer Arithmetic (ISCA), June 2005.
23. M. Oka and M. Suzuoki. Designing and programming the emotion engine. IEEE Micro, 19(6), November 1999.
24. L. Oliker, R. Biswas, J. Borrill, et al. A performance evaluation of the Cray X1 for scientific applications. In Proc. 6th International Meeting on High Performance Computing for Computational Science, 2004.
25. Ornl cray x1 evaluation. http://www.csm.ornl.gov/~dunigan/cray.
26. N. Park, B. Hong, and V. Prasanna. Analysis of memory hierarchy performance of block data layout. In International Conference on Parallel Processing (ICPP), August 2002.
27. D. Pham, S. Asano, M. Bollier, et al. The design and implementation of a first-generation cell processor. ISSCC Dig. Tech. Papers, pages 184-185, February 2005.
28. Sony press release, http://www.scei.co.jp/corporate/release/pdf/050517e. pdf.
29. M. Suzuoki et al. A microprocessor with a 128-bit cpu, ten floating point macs, four floating-point dividers, and an mpeg-2 decoder. IEEE Solid State Circuits, 34(1), November 1999.
30. S. Tomar, S. Kim, N. Vijaykrishnan, et al. Use of local memory for efficient Java execution. In Proceedings of the International Conference on Computer Design, September 2001.
31. R. Vuduc. Automatic Performance Tuning of Sparse Matrix Kernels. PhD thesis, University of California at Berkeley, 2003.
32. D. Wonnacott. Using time skewing to eliminate idle time due to memory bandwidth and network limitations. In International Parallel and Distributed Processing Symposium (IPDPS), 2000.