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Volumn , Issue , 2005, Pages 59-67

The Vector Floating-Point Unit in a Synergistic Processor Element of a CELL Processor

Author keywords

[No Author keywords available]

Indexed keywords

DOUBLE PRECISION OPERATIONS; FLOATING-POINT UNIT; INTEGER OPERATIONS; SYNERGISTIC PROCESSOR ELEMENT;

EID: 27944446098     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (40)

References (20)
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    • (1998) HOTCHIPS 10
    • Diefendorff, K.1    Dubey, P.2    Chochsprung, R.3
  • 5
    • 0028507241 scopus 로고
    • POWER2 floating-point unit: Architecture and implementation
    • Sept.
    • T. N. Hicks, R. E. Fry, and P. E. Harvey. POWER2 floating-point unit: Architecture and implementation. IBM Journal of Research and Development, 38(5):525-536, Sept. 1994.
    • (1994) IBM Journal of Research and Development , vol.38 , Issue.5 , pp. 525-536
    • Hicks, T.N.1    Fry, R.E.2    Harvey, P.E.3
  • 6
    • 0025213823 scopus 로고
    • Leading-zero anticipator (lza) in the ibm rise system/6000 floating point execution unit
    • E. Hokenek and R. K. Montoye. Leading-zero anticipator (lza) in the ibm rise system/6000 floating point execution unit. IBM Journal of Researh and Development, 34(1), 1990.
    • (1990) IBM Journal of Researh and Development , vol.34 , Issue.1
    • Hokenek, E.1    Montoye, R.K.2
  • 7
    • 0034228634 scopus 로고    scopus 로고
    • 2.44-GFLOPS 300-MHz floating-point vector-processing unit for high-performance 3-D graphics computing
    • N. Ide, M. Hirano, Y. Endo, et al. 2.44-GFLOPS 300-MHz Floating-Point Vector-Processing Unit for High-Performance 3-D Graphics Computing. IEEE Journal of Solid-State Circuits, 35(7), 2000.
    • (2000) IEEE Journal of Solid-state Circuits , vol.35 , Issue.7
    • Ide, N.1    Hirano, M.2    Endo, Y.3
  • 10
    • 12944288247 scopus 로고    scopus 로고
    • Vector unit architecture for emotion synthesis
    • A. Kunimatsu, N. Ide, T. Sato, et al. Vector Unit Architecture for Emotion Synthesis. IEEE Micro, 20(2), 2000.
    • (2000) IEEE Micro , vol.20 , Issue.2
    • Kunimatsu, A.1    Ide, N.2    Sato, T.3
  • 12
    • 27944486456 scopus 로고    scopus 로고
    • B. Minor. Personal communication
    • B. Minor. Personal communication.
  • 14
    • 0032633255 scopus 로고    scopus 로고
    • Amd 3dnow! technology: Architecture and implementation
    • S. Oberman, G. Favor, and F. Weber. Amd 3dnow! technology: Architecture and implementation. IEEE Micro, 19(2), 1999.
    • (1999) IEEE Micro , vol.19 , Issue.2
    • Oberman, S.1    Favor, G.2    Weber, F.3
  • 15
    • 28244473720 scopus 로고    scopus 로고
    • A fully-pipelined single-precision floating point unit in the synergistic processor element of a CELL processor
    • paper 2.4
    • H.-J. Oh, S. M. Mueller, C. Jacobi, et al. A Fully-Pipelined Single-Precision Floating Point Unit in the Synergistic Processor Element of a CELL Processor. 2005. IEEE VLSI Conference, paper 2.4.
    • (2005) IEEE VLSI Conference
    • Oh, H.-J.1    Mueller, S.M.2    Jacobi, C.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.