SCIMA: A novel processor architecture for high performance computing

Proceedings - 4th International Conference/Exhibition on High Performance Computing in the Asia-Pacific Region, HPC-Asia 2000

Volumn 1, Issue , 2000, Pages 355-360

  Kondo, M ^a,b   Okawara, H ^b,d   Nakamura, H ^b   Boku, T ^a   Sakai, S ^c  

^a UNIVERSITY OF TSUKUBA   (Japan)

^b UNIVERSITY OF TOKYO   (Japan)

^c UNIVERSITY OF TOKYO   (Japan)

^d FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

IMAGE CODING; MEMORY ARCHITECTURE; PROBLEM SOLVING;

HIGH PERFORMANCE COMPUTING; LINPACK BENCHMARK; PERFORMANCE GAPS; PROCESSOR ARCHITECTURES; PROCESSOR CHIPS; PROCESSOR PERFORMANCE; QCD SIMULATIONS; VLSI ARCHITECTURES;

COMPUTER ARCHITECTURE;

EID: 34247351477     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPC.2000.846577     Document Type: Conference Paper

References (8)

1. http://www.rccp.tsukuba.ac.jp/.
2. http://www.top500.org/.
3. S. Aoki, R. Burkhalter, K. Kanaya, T. Yoshié, T. Boku, H. Nakamura, and Y. Yamashita. Performance of lattice qcd programs on cp-pacs. Parallel Computing 25, 1999.
4. T. Boku, K. Itakura, H. Nakamura, and K. Nakazawa. Cp-pacs : A massively parallel processor for large scale scientific calculations. Proc. of ACM Int'l Conf. on Supercomputing '91, 1997.
5. D. Callahan and A. Porterfield. Data cache performance of supercomputer applications. Proc. of Supercomputing '91, January 1990.
6. S. Coleman and K. S. McKinley. Tile size selection using cache organization and data layout. Proc. of PLDI, June 1995.
7. M. S. Lam, E. E. Rothberg, and M. E. Wolf. The cache performance and optimizations of blocked algorithms. Proc. of ASPLOS-IV, April 1991.
8. P. Panda, H. Nakamura, N. Dutt, and A. Nicolau. Augmenting loop tiling with data alignment for improved cache performance. IEEE Transactions on Computers, 48(2), February 1999.