Analysis of memory hierarchy performance of block data layout

Proceedings of the International Conference on Parallel Processing

Volumn 2002-January, Issue , 2002, Pages 35-44

  Park, Neungsoo ^a   Hong, Bo ^a   Prasanna, V K ^a  

^a University of Southern California ^*  (United States)

Author keywords

Analytical models; Contracts; Degradation; Delay; Monitoring; Optimizing compilers; Parallel processing; Pattern matching; Performance analysis; Tiles

Indexed keywords

ANALYTICAL MODELS; BUFFER STORAGE; CACHE MEMORY; COMPUTER ARCHITECTURE; CONTRACTS; DEGRADATION; MEMORY ARCHITECTURE; MONITORING; PATTERN MATCHING; TILE;

ACCESS PATTERNS; CACHE PERFORMANCE; DATA TRANSFORMATION; DELAY; MEMORY HIERARCHY PERFORMANCE; OPTIMIZING COMPILERS; PARALLEL PROCESSING; PERFORMANCE ANALYSIS;

METADATA;

EID: 24644482622     PISSN: 01903918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICPP.2002.1040857     Document Type: Conference Paper

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