Impact of modern memory subsystems on cache optimizations for stencil computations

Proceedings of the 3rd 2005 ACM SIGPLAN Workshop on Memory Systems Performance, MSP 2005

Volumn , Issue , 2005, Pages 36-43

  Kamil, Shoaib ^a   Husbands, Parry ^a   Oliker, Leonid ^a   Shalf, John ^a   Yelick, Katherine ^a  

^a LAWRENCE BERKELEY NATIONAL LABORATORY   (United States)

Author keywords

Cache blocking; Performance modeling; Prefetch; Stencil

Indexed keywords

CACHE BLOCKING; CACHE OPTIMIZATION; MODERN MICROPROCESSOR; PERFORMANCE MODEL; PREFETCHES; SCIENTIFIC APPLICATIONS; STENCIL; STENCIL COMPUTATIONS;

CACHE MEMORY;

EID: 84958661690     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1111583.1111589     Document Type: Conference Paper

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