Helper threads via virtual multithreading

IEEE Micro

Volumn 24, Issue 6, 2004, Pages 74-82

  Wang, Perry H ^a,c   Collins, Jamison D ^a   Wang, Hong ^a   Kim, Dongkeun ^a   Greene, Bill ^a   Chan, Kai Ming ^b   Yunus, Aamir B ^b   Sych, Terry ^b   Moore, Stephen F ^b   Shen, John P ^c  

^a Intel's Microproc Technology Labs   (United States)

^b Intels Entpr Technol Enabling Grp ^*

^c INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

SIMULTANEOUS MULTITHREAD ARCHITECTURE; VIRTUAL MULTITHREADING;

CACHE MEMORY; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; DATA STORAGE EQUIPMENT; DYNAMIC PROGRAMMING; MATHEMATICAL MODELS; PERFORMANCE;

MICROPROCESSOR CHIPS;

EID: 20144371714     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2004.75     Document Type: Article

References (17)

1. M. Annavaram et al., "Data Prefetching by Dependence Graph Precomputation," Proc. 28th Ann. Int'l Symp. Computer Architecture (ISCA 2001), IEEE CS Press, 2001, pp. 52-61.
2. R.S. Chappell et al., "Simultaneous Subordinate Microthreading (SSMT)," Proc. 26th Ann. Int'l Symp. Computer Architecture (ISCA 1999), IEEE CS Press, 1999, pp. 186-195.
3. J. Collins et al., "Dynamic Speculative Precomputation," Proc. 34th Ann. ACM/IEEE Int'l Symp. Microarchitecture (Micro-34), IEEE CS Press, 2001 pp. 306-317
4. J. Collins et al., "Speculative Precomputation: Long-Range Prefetching of Delinquent Loads," Proc. 28th Ann. Int'l Symp. Computer Architecture (ISCA 01), 2001, pp. 14-25.
5. D. Kim et al., "Physical Experimentation with Prefetching Helper Threads on Intel's HyperThreaded Processors," Int'l Symp. Code Generation and Optimization (CGO 04), IEEE Press, 2004, pp. 27-38
6. D. Kim and D. Yeung, "Design and Evaluation of Compiler Algorithms for Pre-Execution," Proc. 10th Architectural Support for Programming Languages and Operating Systems (ASPLOS 02), ACM Press, 2002, pp. 159-170.
7. S. Liao et al., "Post-Pass Binary Adaptation for Software-Based Speculative Precomputation," Proc. ACM Conf. Programming Language Design and Implementation (PLDI 02), 2002, pp. 117-128.
8. C.K. Luk, "Tolerating Memory Latency through Software-Controlled Pre-Execution in Simultaneous Multithreading Processors," Proc. 28th Ann. Int'l Symp. Computer Architecture (ISCA 01), IEEE CS Press, pp. 40-51.
9. A. Roth and G. Sohi, "Speculative Data-Driven Multithreading," Proc. 7th Int'l Symp. High-Performance Computer Architecture (HPCA 01), IEEE CS Press, 2001, pp. 37-48.
10. Y. Song and M. Dubois, Assisted Execution Technical Report CENG 98-25, Dept. Electrical Eng. Systems, Univ. of Southern California Oct. 1998.
11. H. Wang et al., "Speculative Precomputation: Exploring Use of Multithreading Technology for Latency," Intel Tech. J., Feb. 2002 Feb. 14, 2002, vol. 6, no. 1.
12. P. Wang et al., "Memory Latency-Tolerance Approaches for Itanium Processors: Out-of-Order Execution vs. Speculative Precomputation," Proc. 8th Int'l Symp. High-Performance Computer Architecture (HPCA 02), IEEE CS Press, 2002, pp. 187-196.
13. Intel Itanium 2 Processor Reference Manual for Software Development and Optimization, Intel Corp., June 2002.
14. Intel Itanium Architecture Software Developer's Manual, Intel Corp., Oct. 2002.
15. J. Bharadwaj et al., "The Intel IA-64 Compiler Code Generator," IEEE Micro, vol. 20, no. 5, Sept.-Oct. 2000, pp. 44-53.
16. R. Krishnaiyer et al., "An Advanced Optimizer for the IA-64 Architecture," IEEE Micro, vol. 20, no. 6, Nov.-Dec. 2000, pp. 60-68.
17. M. Poess and C. Floyd, " New TPC Bench-marks for Decision Support and Web Commerce," http://www.tpc.org.