Zero-aware asymmetric SRAM cell for reducing cache power in writing zero

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 12, Issue 8, 2004, Pages 827-836

  Chang, Yen Jen ^a   Lai, Feipei ^b   Yang, Chia Lin ^b  

^a NATIONAL CHUNG HSING UNIVERSITY   (Taiwan)

^b NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

Asymmetric; Cache write power; Low power; On chip caches; SRAM cell; Zero aware

Indexed keywords

BENCHMARKING; CACHE MEMORY; COMPUTER SOFTWARE; DATA REDUCTION; ELECTRIC POTENTIAL; ELECTRIC POWER UTILIZATION; EMBEDDED SYSTEMS; ENERGY DISSIPATION; MICROPROCESSOR CHIPS;

CACHE WRITE POWER; LOW-POWER TECHNIQUES; ON-CHIP CACHES; PULSED-WORDLINE TECHNIQUE;

STATIC RANDOM ACCESS STORAGE;

EID: 4043144988     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.831471     Document Type: Article

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