A case for asymmetric-cell cache memories

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 13, Issue 7, 2005, Pages 877-881

  Moshovos, Andreas ^a   Falsafi, Babak ^b   Najm, Farid N ^a   Azizi, Navid ^a  

^a UNIVERSITY OF TORONTO   (Canada)

^b CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

Cache memories; Computer architecture; High performance; Leakage power reduction

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SIMULATION; LEAKAGE CURRENTS; MATHEMATICAL MODELS; STATIC RANDOM ACCESS STORAGE;

ASYMMETRIC-CELLS; HIGH PERFORMANCE; LEAKAGE POWER REDUCTION; MEMORY VALUE CONTENT;

BUFFER STORAGE;

EID: 27644488999     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2005.850127     Document Type: Article

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