Compiler-guided leakage optimization for banked scratch-pad memories

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 13, Issue 10, 2005, Pages 1136-1146

  Kandemir, M ^a   Irwin, M J ^a   Chen, G ^a   Kolcu, I ^a  

^a The Pennsylvania State University   (United States)

Author keywords

Aphilipp; Banked scratch pad memories; Compiler based leakage energy optimization; Compiler guided memory data layout optimization; Data migration; Low leakage state; Low power state; On chip scratch pad memories; SPM bank idleness

Indexed keywords

DATA ACQUISITION; ENERGY UTILIZATION; MICROPROCESSOR CHIPS; OPTIMIZATION; PROGRAM COMPILERS;

APHILIPP; BANKED SCRATCH-PAD MEMORIES; LOW-LEAKAGE STATE; LOW-POWER STATE; ON-CHIP SCRATCH-PAD MEMORIES;

DATA STORAGE EQUIPMENT;

EID: 31144441199     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2005.859478     Document Type: Article

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