Threshold-voltage modeling of body-tied FinFETs (Bulk FinFETs)

IEEE Transactions on Electron Devices

Volumn 54, Issue 3, 2007, Pages 537-545

  Choi, Byung Kil ^a   Han, Kyoung Rok ^a   Kim, Young Min ^a   Park, Young June ^b   Lee, Jong Ho ^b  

^a Kyungpook National University   (South Korea)

^b Seoul National University   (South Korea)

Author keywords

Body tied; Bulk FinFET; Corner effect; Modeling; Narrow width effect (NWE); Short channel effect (SCE); Threshold voltage

Indexed keywords

COMPUTER SIMULATION; GATES (TRANSISTOR); SILICON WAFERS; THRESHOLD VOLTAGE;

BULK FINFET; NARROW-WIDTH EFFECT; SHORT-CHANNEL EFFECT;

MOSFET DEVICES;

EID: 33947614660     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2006.890374     Document Type: Article

References (25)

1. International Technology Roadmap for Semiconductors, 2005. [Online]. Available: http://public.itrs.net
2. Y.-K. Choi, K. Asano, N. Lindert, V. Subramanian, T.-J. King, J. Bokor, and C. Hu, "Ultra-thin body SOI MOSFET for deep-sub-tenth micron era," in IEDM Tech. Dig., Dec. 1999, pp. 919-921.
3. G. A. Kathawala, B. Winstead, and U. Ravaidi, "Monte Carlo simulation of double-gate MOSFETs," IEEE Trans. Electron Devices, vol. 50, no. 12, pp. 2467-2473, Dec. 2003.
4. Q. Chen, E. M. Harrel, and J. D. Meindl, "A physical short-channel threshold voltage model for undoped symmetric double-gate MOSFETs," IEEE Trans. Electron Devices, vol. 50, no. 7, pp. 1631-1637, Jul. 2003.
5. B. Doyle, B. Boyanov, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, R. Rios, and R. Chan, "Tri-gate fully-depleted CMOS transistor: Fabrication, design and layout," in VLSI Symp. Tech. Dig., Jun. 2003, pp. 133-134.
6. J. Kedzierski, M. Ieong, E. Nowak, T. S. Kanarsky, Y. Zhang, R. Roy, D. Boyd, D. Fried, and H.-S. P. Wong, "Extension and source/drain design for high-performance FinFET devices," IEEE Trans. Electron Devices, vol. 50, no. 4, pp. 952-958, Apr. 2003.
7. E. J. Nowak, T. Ludwig, I. Aller, J. Kedzierski, M. Ieong, B. Rainey, M. Breitwisch, V. Gernhoefer, J. Keinert, and D. M. Fried, "Scaling beyond the 65 nm node with FinFET-DGCMOS," in Proc. IEEE Custom Integr. Circuit, Sep. 2003, pp. 339-342.
8. X. Huang, W.-C. Lee, C. Kuo, D. Hisamotom, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J. King, and C. Hu, "Sub-50 nm p-channel FinFET," IEEE Trans. Electron Devices, vol. 48, no. 5, pp. 880-886, May 2003.
9. H.-Y. Chen, C.-C. Huang, C.-C. Huang, C.-Y. Chang, Y.-C. Yeo, F.-L Yang, and C. Hu, "Scaling of CMOS FinFETs toward 10 nm," in VLSI Symp. Tech. Dig., Oct. 2003, pp. 6-8.
10. B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C.-Y. Yang, C. Tabery, C. Ho, Q. Xiang, T.-J. King, J. Bokor, C. Hu, M.-R. Lin, and D. Kyser, "FinFET scaling to 10 nm gate length," in IEDM Tech. Dig., Dec. 2002, pp. 10.2.1-10.2.4.
11. G. A. Kathawala and U. Ravaioli, "3-D Monte Carlo simulation of FinFETs," in IEDM Tech. Dig., Dec. 2003, pp. 29.2.1-29.2.4.
12. T.-S. Park, E. Yoon, and J.-H. Lee, "A 40 nm body-tied FinFET (OMEGA MOSFET) using bulk Si wafer," Physica E, vol. 19, no. 1, pp. 6-12, Jul. 2003.
13. T. Park, S. Choi, D. H. Lee, J. R. Yoo, B. C. Lee, J. Y. Kim, C. G. Lee, K. K. Chi, S. H. Hong, S. J. Hyun, Y. G. Shin, J. N. Han, I. S. Park, U. I. Chung, J. T. Moon, E. Yoon, and J. H. Lee, "Fabrication of body-tied FinFETs (Omega MOSFETs) using bulk Si wafers," in VLSI Symp. Tech. Dig., 2003, pp. 135-136.
14. T. Park, H. J. Choe, S. Y. Han, S.-M. Jung, B. Y. Nam, O. I. Kwon, J. N. Han, H. S. Kang, M. C. Chae, G. S. Yeo, S. W. Lee, D. Y. Lee, D. Park, K. Kim, E. Yoon, and J. H. Lee, "Static noise margin of the full DG-CMOS SRAM cell using bulk FinFETs (Omega MOSFETs)," in IEDM Tech. Dig., Dec. 2003, pp. 27-30.
15. J.-H. Lee, T.-S. Park, E. Yoon, and Y. J. Park, "Simulation study of a new body-tied FinFETs (Omega MOSFETs) using bulk Si wafers," in Proc. Si Nanoelectron. Tech. Dig., 2003, pp. 102-103.
16. K.-H. Back, K.-R. Han, and J.-H. Lee, "Corner effect in body-tied double/triple-gate MOSFETs implemented on bulk Si wafers," in Proc. Si Nanoelectron. Tech. Dig., 2004, pp. 47-48.
17. J. G. Fossum, J.-W. Yang, and V. P. Trivedi, Σuppression of corner effect in triple-gate MOSFETs," IEEE Electron Device Lett., vol. 24, no. 12, pp. 745-747, Dec. 2003.
18. SILVACO International, ATLAS User's Manual, 2006. [Online]. Available: http://www.silvaco.com
19. L. D. Yau, "A simple theory to predict the threshold voltage of short channel IGFET's," Solid State Electron., vol. 17, no. 10, pp. 1059-1063, Oct. 1974.
20. L. A. Akers and J. J. Sanchez, "Threshold voltage models of short, narrow and small geometry MOSFET's: A review," Solid State Electron., vol. 25, no. 7, pp. 621-641, Jul. 1982.
21. R. S. Muller and T. I. Kamins, Device Electronics for Integrated Circuits, 2nd ed. Hoboken, NJ: Wiley, 1986, p. 443.
22. S. Veeraraghavan and J. G. Fossum, "A physical short-channel model for the thin-film SOI MOSFET applicable to device and circuit CAD," IEEE Trans. Electron Devices, vol. 35, no. 11, pp. 1866-1875, Nov. 1988.
23. R. Shrivastava and K. Fitzpatrick, "A simple model for the overlap capacitance of a VLSI MOS device," IEEE Trans. Electron Devices, vol. ED-29, no. 12, pp. 1870-1875, Dec. 1982.
24. C. P. Auth and J. Plummer, "A simple model for threshold voltage of surrounding-gate MOSFET's," IEEE Trans. Electron Devices, vol. 45, no. 11, pp. 2381-2383, Nov. 1998.
25. E. Lyumkis, R. Mickevicius, O. Penzin, B. Polsky, K. El Sayed, A. Wettstein, and W. Fichtner, "Simulations of ultrathin, ultrashort double-gated MOSFETs with the density gradient transport model," in Proc. SISPAD, Sep. 2002, pp. 271-274.