A 40 nm body-tied FinFET (OMEGA MOSFET) using bulk Si wafer

Physica E: Low-Dimensional Systems and Nanostructures

Volumn 19, Issue 1-2, 2003, Pages 6-12

  Park, Tai Su ^a   Yoon, Euijoon ^a   Lee, Jong Ho ^b  

^a Seoul National University   (South Korea)

^b Kyungpook National University   (South Korea)

Author keywords

Body tied; Bulk Si wafer; DG MOSFET; FinFET; MOSFET; Nano

Indexed keywords

COMPUTER SIMULATION; GATES (TRANSISTOR); SILICON ON INSULATOR TECHNOLOGY; SILICON WAFERS;

SPACER TECHNOLOGY;

MOSFET DEVICES;

EID: 0042009672     PISSN: 13869477     EISSN: None     Source Type: Journal    
DOI: 10.1016/S1386-9477(03)00285-6     Document Type: Conference Paper

References (5)

1. J. Kedzierski, et al., Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation, International Electron Devices Meeting, Technical Digest, 2002, pp. 247-250.
2. B. Yu, et al., FinFET scaling to 10 nm gate length, International Electron Devices Meeting, Technical Digest, 2002, pp. 251-254.
3. Jean-Pierre Colinge, Silicon-on-Insulator Technology: Materials to VLSI, Kluwer Academic Publishers, Dordrecht, 1991.
4. Jong-Ho Lee, Korean patent filed, File No. 10-2002-0005325, January 2002.
5. TM User's Manual, Version 5.2.0.R, 2000.