Scaling of CMOS FinFETs towards 10 nm

International Symposium on VLSI Technology, Systems, and Applications, Proceedings

Volumn 2003-January, Issue , 2003, Pages 46-48

  Chen, Hao Yu ^a   Huang, Chien Chao ^a   Huang, Cheng Chuan ^a   Chang, Chang Yun ^a   Yeo, Yee Chia ^a   Yang, Fu Liang ^a   Hu, Chenming ^a  

^a TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS;

CMOS FINFETS; DEVICE SIMULATIONS; DUAL DOPED; GATE LENGTH; HIGH DRIVE CURRENT; MID-GAP GATE; OFF-STATE LEAKAGE; PERFORMANCE PARAMETERS;

MOSFET DEVICES;

EID: 33847118685     PISSN: 19308868     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTSA.2003.1252548     Document Type: Conference Paper

References (8)

1. International Technology Roadmap for Semiconductors, SIA, 2001.
2. D. Hisamoto, IEDM, p. 429, 2001.
3. Y.-K. Choi et al., IEDM, p. 421, 2001.
4. F.-L. Yang et al, Symp. VLSI Tech., p. 109, 2001.
5. Q. Xiang et al, Symp. VLSI Tech., p. 23, 2001.
6. S. Inaba et al. IEDM, p. 641, 2001.
7. J. Kedzierski et al, IEDM, p. 437, 2001.
8. S. Fung et al. JEDM, p. 629, 2001.