BUSpec: A framework for generation of verification aids for standard bus protocol specifications

Integration, the VLSI Journal

Volumn 40, Issue 3, 2007, Pages 285-304

  Pal, Bhaskar ^a   Banerjee, Ansuman ^a   Dasgupta, Pallab ^a   Chakrabarti, P P ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY   (India)

Author keywords

Assertion based verification; Bus functional models; Protocol validation; Verification intellectual property

Indexed keywords

HIERARCHICAL SYSTEMS; INTERFACES (COMPUTER); MATHEMATICAL MODELS; NETWORK PROTOCOLS;

ASSERTION BASED VERIFICATION; BUS FUNCTIONAL MODELS; PROTOCOL VALIDATION; VERIFICATION INTELLECTUAL PROPERTY;

BUSBARS;

EID: 33947409155     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.vlsi.2005.12.004     Document Type: Article

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