On the use of a high-level fault model to check properties incompleteness

Proceedings - 1st ACM and IEEE International Conference on Formal Methods and Models for Co-Design, MEMOCODE 2003

Volumn , Issue , 2003, Pages 145-152

  Fummi, F ^a   Pravadelli, G ^a   Fedeli, A ^b   Rossi, U ^b   Toto, F ^b  

^a UNIVERSITY OF VERONA   (Italy)

^b STMICROELECTRONICS   (Italy)

Author keywords

Algorithm design and analysis; Automatic test pattern generation; Design engineering; Digital systems; Explosions; Formal verification; Logic design; Mathematical model; Safety; State space methods

Indexed keywords

ACCIDENT PREVENTION; AUTOMATIC TEST PATTERN GENERATION; DESIGN; EXPLOSIONS; FORMAL METHODS; FORMAL VERIFICATION; LOGIC DESIGN; MATHEMATICAL MODELS; STATE SPACE METHODS;

ALGORITHM DESIGN AND ANALYSIS; COVERAGE METRICS; DESIGN ENGINEERING; DIGITAL SYSTEM; FORMAL PROPERTIES; HIGH-LEVEL FAULT; HIGH-LEVEL FAULT MODELS;

MODEL CHECKING;

EID: 84943637314     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MEMCOD.2003.1210099     Document Type: Conference Paper

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