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Volumn , Issue , 2000, Pages 196-200
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Formal verification of an IBM CoreConnect processor local bus arbiter core
a
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Author keywords
[No Author keywords available]
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Indexed keywords
BOOLEAN FUNCTIONS;
COMPUTER ARCHITECTURE;
COMPUTER HARDWARE DESCRIPTION LANGUAGES;
DATA STRUCTURES;
GRAPH THEORY;
INTERCONNECTION NETWORKS;
LOGIC DESIGN;
MICROPROCESSOR CHIPS;
DEVICE CONTROL REGISTER BUS;
FORMAL VERIFICATION;
ON-CHIP PERIPHERAL BUS;
PROCESSOR LOCAL BUS;
NETWORK PROTOCOLS;
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EID: 0033684179
PISSN: 0738100X
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1145/337292.337384 Document Type: Conference Paper |
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Times cited : (38)
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References (13)
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