Specification and formal verification of interconnect bus protocols

Midwest Symposium on Circuits and Systems

Volumn 1, Issue , 2000, Pages 378-382

  Ivanov, Lubomir ^a   Nunna, Ramakrishna ^b  

^a IONA COLLEGE   (United States)

^b CALIFORNIA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; PARALLEL PROCESSING SYSTEMS; POLYNOMIALS;

FORMAL VERIFICATION; HANDSHAKING PROTOCOL; INTERCONNECT BUS PROTOCOLS; SYMBOLIC MODEL CHECKING;

NETWORK PROTOCOLS;

EID: 0034464817     PISSN: None     EISSN: None     Source Type: Journal    
DOI: 10.1109/MWSCAS.2000.951664     Document Type: Article

References (12)

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8. Formal verification with series-parallel posets of globally-iterated/locally-non-iterated systems
9. Formal verification: A new partial order approach
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11. Formal verification of the PCI local bus: A step towards IP core based system-on-chip design verification