A specification methodology by a collection of compact properties as applied to the Intel® Itanium™ processor bus protocol

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2144, Issue , 2001, Pages 340-354

  Shimizu, Kanna ^a   Dill, David L ^a   Chou, Ching Tsun ^b  

^a STANFORD UNIVERSITY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FORMAL LOGIC; SYSTEM BUSES;

BUS PROTOCOL; DATA PHASIS; INTERFACE SPECIFICATION; PROCESSOR BUS; SIGNAL LEVEL; SIMULATION ENVIRONMENT; SPECIFICATION METHODOLOGIES; STANDARD BUS;

FORMAL SPECIFICATION;

EID: 77953895494     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-44798-9_27     Document Type: Conference Paper

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