메뉴 건너뛰기




Volumn 53, Issue 9, 2006, Pages 2091-2096

Analytical modeling of output conductance in long-channel halo-doped MOSFETs

Author keywords

Compact model; Halo; MOSFET; Output resistance degradation

Indexed keywords

ANALYTICAL DERIVATION; COMPACT MODELS; HALO TRANSISTORS; OUTPUT RESISTANCE DEGRADATION;

EID: 33947113783     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2006.880371     Document Type: Article
Times cited : (23)

References (19)
  • 1
    • 0033325117 scopus 로고    scopus 로고
    • Device issues in the integration of analog/RF functions in deep submicron digital CMOS
    • D. Buss, "Device issues in the integration of analog/RF functions in deep submicron digital CMOS," in IEDM Tech. Dig, 1999, pp. 423-425.
    • (1999) IEDM Tech. Dig , pp. 423-425
    • Buss, D.1
  • 2
    • 0028746293 scopus 로고
    • A 0.1μm CMOS technology with Tilt-Implanted Punch through Stopper(TIPS)
    • T. Hori, "A 0.1μm CMOS technology with Tilt-Implanted Punch through Stopper(TIPS)," in IEDM Tech. Dig., 1994, pp. 75-78.
    • (1994) IEDM Tech. Dig , pp. 75-78
    • Hori, T.1
  • 3
    • 0025575449 scopus 로고
    • A novel source-to-drain non-uniformly doped channel (NUDC) MOSFET for high current drivability and threshold voltage controllability
    • Y. Okumura et al., "A novel source-to-drain non-uniformly doped channel (NUDC) MOSFET for high current drivability and threshold voltage controllability," in IEDM Tech. Dig., 1990, pp. 391-394.
    • (1990) IEDM Tech. Dig , pp. 391-394
    • Okumura, Y.1
  • 4
    • 84886447961 scopus 로고    scopus 로고
    • CMOS devices below 0.1 μm: How high will performance go?
    • Y. Taur et al., "CMOS devices below 0.1 μm: How high will performance go?," in IEDM Tech Dig., 1997, pp. 215-218.
    • (1997) IEDM Tech Dig , pp. 215-218
    • Taur, Y.1
  • 5
    • 0035478372 scopus 로고    scopus 로고
    • Design considerations for 25 nm MOSFET devices
    • Oct
    • S. Saha, "Design considerations for 25 nm MOSFET devices," Solid State Electron., vol. 45, no. 10, pp. 1851-1857, Oct. 2001.
    • (2001) Solid State Electron , vol.45 , Issue.10 , pp. 1851-1857
    • Saha, S.1
  • 6
    • 0030655664 scopus 로고    scopus 로고
    • Modeling reverse short channel and narrow width effects in small size MOSFETs for circuit simulation
    • Y. Cheng et al., "Modeling reverse short channel and narrow width effects in small size MOSFETs for circuit simulation," in Proc. SISPAD, 1997, pp. 249-252.
    • (1997) Proc. SISPAD , pp. 249-252
    • Cheng, Y.1
  • 7
    • 0036772199 scopus 로고    scopus 로고
    • Impurity-profile-based threshold-voltage model of pocket-implanted MOSFETs for circuit simulation
    • Oct
    • H. Ueno et al., "Impurity-profile-based threshold-voltage model of pocket-implanted MOSFETs for circuit simulation," IEEE Trans. Electron Devices, vol. 49, no. 10, pp. 1783-1789, Oct. 2002.
    • (2002) IEEE Trans. Electron Devices , vol.49 , Issue.10 , pp. 1783-1789
    • Ueno, H.1
  • 8
    • 0037001792 scopus 로고    scopus 로고
    • Analytical subthreshold surface potential model for pocket n-MOSFETs
    • Dec
    • Y.-S. Pang et al., "Analytical subthreshold surface potential model for pocket n-MOSFETs," IEEE Trans. Electron Devices, vol. 49, no. 12, pp. 2209-2216, Dec. 2002.
    • (2002) IEEE Trans. Electron Devices , vol.49 , Issue.12 , pp. 2209-2216
    • Pang, Y.-S.1
  • 9
    • 84907891995 scopus 로고    scopus 로고
    • Implications of pocket optimisation on analog performance in deep sub-micron CMOS
    • R. F. M. Roes et al., "Implications of pocket optimisation on analog performance in deep sub-micron CMOS," in Proc. ESSDERC, 1999, pp. 176-179.
    • (1999) Proc. ESSDERC , pp. 176-179
    • Roes, R.F.M.1
  • 10
    • 0033325337 scopus 로고    scopus 로고
    • Modeling of pocket implanted MOSFETs for anomalous analog behavior
    • K. M. Cao et al., "Modeling of pocket implanted MOSFETs for anomalous analog behavior," in IEDM Tech. Dig., 1999, pp. 171-174.
    • (1999) IEDM Tech. Dig , pp. 171-174
    • Cao, K.M.1
  • 11
    • 0033280393 scopus 로고    scopus 로고
    • Transistor design issues in integrating analog functions with high performance digital MOS
    • A. Chatterjee et al., "Transistor design issues in integrating analog functions with high performance digital MOS," in VLSI Symp. Tech. Dig., 1999, p. 147.
    • (1999) VLSI Symp. Tech. Dig , pp. 147
    • Chatterjee, A.1
  • 12
    • 0036929393 scopus 로고    scopus 로고
    • A three-transistor threshold voltage model for halo processes
    • R. Rios et al., "A three-transistor threshold voltage model for halo processes," in IEDM Tech. Dig., 2002, pp. 113-116.
    • (2002) IEDM Tech. Dig , pp. 113-116
    • Rios, R.1
  • 13
    • 0029306018 scopus 로고
    • Channel profile engineering for MOSFETs with 100 nm channel lengths
    • May
    • J. B. Jacobs et al., "Channel profile engineering for MOSFETs with 100 nm channel lengths," IEEE Trans. Electron Devices, vol. 42, no. 5, pp. 870-875, May 1995.
    • (1995) IEEE Trans. Electron Devices , vol.42 , Issue.5 , pp. 870-875
    • Jacobs, J.B.1
  • 14
    • 0029714797 scopus 로고    scopus 로고
    • Asymmetrically-doped buried layer (ADB) structure CMOS for low-voltage mixed analog-digital applications
    • M. Miyamoto et al., "Asymmetrically-doped buried layer (ADB) structure CMOS for low-voltage mixed analog-digital applications," in VLSI Symp. Tech. Dig., 1996, p. 102.
    • (1996) VLSI Symp. Tech. Dig , pp. 102
    • Miyamoto, M.1
  • 17
    • 0028446654 scopus 로고
    • PCIM: A physically based continuous short-channel IGFET model for circuit simulations
    • Jun
    • N. Arora et al., "PCIM: A physically based continuous short-channel IGFET model for circuit simulations," IEEE Trans. Electron Devices, vol. 41, no. 6, pp. 988-997, Jun. 1994.
    • (1994) IEEE Trans. Electron Devices , vol.41 , Issue.6 , pp. 988-997
    • Arora, N.1
  • 18
    • 4544385361 scopus 로고    scopus 로고
    • A comparison of State-of-the-Art NMOS and SiGe HBT devices for Analog/Mixed-signat/RF circuit applications
    • K. Kuhn et al., "A comparison of State-of-the-Art NMOS and SiGe HBT devices for Analog/Mixed-signat/RF circuit applications," in VLSI Symp. Tech. Dig., 2004, p. 224.
    • (2004) VLSI Symp. Tech. Dig , pp. 224
    • Kuhn, K.1
  • 19
    • 84886448146 scopus 로고    scopus 로고
    • Accurate drain conductance modeling for distortion analysis in MOSFETs
    • R. Van Langevelde et al., "Accurate drain conductance modeling for distortion analysis in MOSFETs," in IEDM Tech. Dig., 1997, pp. 313-316.
    • (1997) IEDM Tech. Dig , pp. 313-316
    • Van Langevelde, R.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.