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Defect classes-an overdue paradigm for CMOS IC testing
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Variance Reduction Using Wafer Patterns in IDDQ Data
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W.R. Daasch, J. McNames, D. Bockelman, K. Cota, and R. Madge, "Variance Reduction Using Wafer Patterns in IDDQ Data," Proceedings of International Test Conference, pp. 189-198, October 2000
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R. Madge, M. Rehani, K. Cota, and R. Daasch, Statistical Post-Processing at Wafer Sort - An Alternative to Burn-in and a Manufacturable Solution to Test Limit Setting for Sub-micron Technologies, IEEE Proceedings 20th VLSI Test Symposium, pp. 69-74, April 2002
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Screening MinVDD Outliers Using Feed-Forward Voltage Testing
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Testing for Resistive Opens and Stuck Opens
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On comparison of NCR effectiveness with a reduced I/sub DDQ/ vector set
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S. Sabade, and D.M.H. Walker, "On comparison of NCR effectiveness with a reduced I/sub DDQ/ vector set," Proceedings VLSI Test Symposium, pp. 65-70, April 2004
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Data-driven models for Statistical Testing: Measurements, Estimates and Residuals
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