Design of robust, energy-efficient full adders for deep-submicrometer design using hybrid-CMOS logic style

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 14, Issue 12, 2006, Pages 1309-1321

  Goel, Sumeer ^a,b   Kumar, Ashok ^a,b   Bayoumi, Magdy A ^a,b  

^a IEEE   (United States)

^b University of Louisiana at Lafayette   (United States)

Author keywords

Adders; Deep submicrometer design; Hybrid CMOS design style; Low power; Noise

Indexed keywords

CMOS LOGIC STYLE CIRCUITS; DEGREE OF DESIGN FREEDOM; ENERGY EFFICIENT FULL ADDERS; LOW ENERGY OPERATIONS;

ADDERS; DEGREES OF FREEDOM (MECHANICS); ELECTRIC POTENTIAL; ENERGY EFFICIENCY; MACHINE DESIGN; PROBLEM SOLVING;

CMOS INTEGRATED CIRCUITS;

EID: 33846632307     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2006.887807     Document Type: Article

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