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Volumn 5, Issue , 2003, Pages

A novel hybrid pass logic with static CMOS output drive full-adder cell

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; BUFFER STORAGE; COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES;

EID: 0038082042     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (141)

References (8)
  • 1
    • 84941857371 scopus 로고
    • Low-power design techniques for high-performance CMOS adders
    • Jun.
    • U. Ko, P. Balasara and W. Lee, "Low-power design techniques for high-performance CMOS adders," IEEE Trans. on VLSI Syst., vol. 3, no. 2, pp.327-333, Jun 1995.
    • (1995) IEEE Trans. on VLSI Syst. , vol.3 , Issue.2 , pp. 327-333
    • Ko, U.1    Balasara, P.2    Lee, W.3
  • 2
    • 0031189144 scopus 로고    scopus 로고
    • Low-power logic styles: CMOS versus pass-transistor logic
    • Jul.
    • R. Zimmermann and W. Fichtner, "Low-power logic styles: CMOS versus pass-transistor logic," IEEE J. of Solid-State Circuits, vol. 32, no. 7, pp. 1079-1090, Jul 1997.
    • (1997) IEEE J. of Solid-State Circuits , vol.32 , Issue.7 , pp. 1079-1090
    • Zimmermann, R.1    Fichtner, W.2
  • 4
    • 0036476973 scopus 로고    scopus 로고
    • Performance analysis of low-power 1-bit CMOS full adder cells
    • Feb.
    • A. Shams, T. Darwish and M. Byoumi, "Performance analysis of low-power 1-bit CMOS full adder cells," IEEE Trans. on VLSI Syst., vol. 10, no. 1, pp. 20-29, Feb 2002.
    • (2002) IEEE Trans. on VLSI Syst. , vol.10 , Issue.1 , pp. 20-29
    • Shams, A.1    Darwish, T.2    Byoumi, M.3
  • 6
    • 0026866556 scopus 로고
    • A new design of the CMOS full adder
    • May
    • N. Zhuang and H. Hu, " A new design of the CMOS full adder," IEEE J. of Solid-State Circuits, vol. 27, no. 5, pp. 840-844, May 1992.
    • (1992) IEEE J. of Solid-State Circuits , vol.27 , Issue.5 , pp. 840-844
    • Zhuang, N.1    Hu, H.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.