A low-leakage 2.5GHz skewed CMOS 32b adder for nanometer CMOS technologies

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Von Arnim, Klaus ^a,b   Seegebrecht, Peter ^b   Thewes, Roland ^a   Pacha, Christian ^a  

^a INFINEON TECHNOLOGIES AG   (Germany)

^b UNIVERSITY OF KIEL   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; AMPLIFIERS (ELECTRONIC); DATA REDUCTION; FLIP FLOP CIRCUITS; LEAKAGE CURRENTS; LOGIC GATES; NANOSTRUCTURED MATERIALS;

DATA PATH; PARALLEL PREFIX ADDER; SINGLE-CYCLE ACTIVATION;

CMOS INTEGRATED CIRCUITS;

EID: 28144434543     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. J. Tschanz et al., "Dynamic-Sleep Transistor and Body Bias for Active Leakage Power Control of Microprocessors," ISSCC Dig. Tech. Papers, pp. 102-103, Feb., 2003.
2. S. F. Huang et al., "High performance 50nm CMOS Devices for Microprocessor and Embedded Processor Core Applications," IEDM Tech. Dig., pp. 237-240, Dec., 2001.
3. A. Solomatnikov et al., "Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family," Int. Conf. Computer Design, pp. 241-246, Sept., 2000.
4. B. Nikolic et al., "Sense Amplifier-Based Flip-Flop," ISSCC Dig. Tech. Papers, pp. 282-283, Feb., 1999.