Validating the intel® Pentium® 4 microprocessor

Proceedings of the International Conference on Dependable Systems and Networks

Volumn , Issue , 2001, Pages 493-498

  Bentley, Bob ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; DATA TRANSFER; FORMAL LOGIC; INTERFACES (COMPUTER);

RAPID EXECUTION ENGINE;

MICROPROCESSOR CHIPS;

EID: 0035790417     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSN.2001.941434     Document Type: Conference Paper

References (5)

1. Clark, D, "Bugs Are Good: A Problem-Oriented Approach To The Management Of Design Engineering", Research-Technology Management, 33(3), May 1990, pp. 23-27,.
2. Ho, R, Yang, H, Horowitz, M, and Dill, D: "Architecture Validation for Processors", ISCA 95: Internaltional Conference on Computer Architecture, June 1995
3. Fournier, L, Arbetman, Y and Levinger, M: "Functional Verification Methodology for Microprocessors Using the Genesys Test-Program Generator - Application to the x86 Microprocessors Family", Proceedings of the Design Automation and Test in Europe Conference and Exhibition (DATE99), March 1999.
4. Bentley, R, and Milburn, B, "Analysis of Pentium® Pro Processor Bugs", Intel Design and Test Technology Conference, June 1996.
5. Zucker, R, "Bug Root Cause Analysis for Willamette", Intel Design and Test Technology Conference, August 2000.