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Volumn , Issue , 2004, Pages 260-265

On test and diagnostics of flash memories

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COSTS; DESIGN FOR TESTABILITY; FAILURE ANALYSIS; FIELD PROGRAMMABLE GATE ARRAYS; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; RANDOM ACCESS STORAGE; ULTRAVIOLET RADIATION;

EID: 13244277458     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (6)

References (15)
  • 1
    • 0242359074 scopus 로고    scopus 로고
    • RAMSES-FT: A fault simulator for flash memory testing and diagnostics
    • Monterey, California, Apr.
    • K.-L. Cheng, J.-C. Yeh, C.-W. Wang, C.-T. Huang, and C.-W. Wu. RAMSES-FT: A fault simulator for flash memory testing and diagnostics. In Proc. IEEE VLSI Test Symp. (VTS), pages 281-286, Monterey, California, Apr. 2002.
    • (2002) Proc. IEEE VLSI Test Symp. (VTS) , pp. 281-286
    • Cheng, K.-L.1    Yeh, J.-C.2    Wang, C.-W.3    Huang, C.-T.4    Wu, C.-W.5
  • 2
  • 3
    • 0024124138 scopus 로고
    • Fault modeling and test algorithm development for static random access memories
    • R. Dekker, F. Beenker, and L. Thijssen. Fault modeling and test algorithm development for static random access memories. In Proc. Int. Test Conf. (ITC), pages 343-352, 1988.
    • (1988) Proc. Int. Test Conf. (ITC) , pp. 343-352
    • Dekker, R.1    Beenker, F.2    Thijssen, L.3
  • 4
    • 0034505514 scopus 로고    scopus 로고
    • An experimental analysis of spot defects in SRAMs: Realistic fault models and tests
    • Taipei, Dec.
    • S. Hamdioui and A. J. van de Goor. An experimental analysis of spot defects in SRAMs: realistic fault models and tests. In Proc. Ninth IEEE Asian Test Symp. (ATS), pages 131-138, Taipei, Dec. 2000.
    • (2000) Proc. Ninth IEEE Asian Test Symp. (ATS) , pp. 131-138
    • Hamdioui, S.1    Van De Goor, A.J.2
  • 7
    • 0034995342 scopus 로고    scopus 로고
    • Flash memory disturbances: Modeling and test
    • Marina Del Rey, California, Apr.
    • M. G. Mohammad and K. K. Saluja. Flash memory disturbances: modeling and test. In Proc. IEEE VLSI Test Symp. (VTS), pages 218 -224, Marina Del Rey, California, Apr. 2001.
    • (2001) Proc. IEEE VLSI Test Symp. (VTS) , pp. 218-224
    • Mohammad, M.G.1    Saluja, K.K.2
  • 8
    • 13244286069 scopus 로고    scopus 로고
    • Electrical model for program disturb faults in non-volatile memories
    • New Delhi, India, Jan.
    • M. G. Mohammad and K. K. Saluja. Electrical model for program disturb faults in non-volatile memories. In Proc. 16th Int. Conf. VLSI Design, pages 217 -222, New Delhi, India, Jan. 2003.
    • (2003) Proc. 16th Int. Conf. VLSI Design , pp. 217-222
    • Mohammad, M.G.1    Saluja, K.K.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.