Considering run-time reconfiguration overhead in task graph transformations for dynamically reconfigurable architectures

Proceedings - 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2005

Volumn 2005, Issue , 2005, Pages 273-274

  Banerjee, Sudarshan ^a   Bozorgzadeh, Elaheh ^a   Dutt, Nikil ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONSTRAINT THEORY; GRAPH THEORY; MATHEMATICAL TRANSFORMATIONS; MULTIPROCESSING SYSTEMS; RESOURCE ALLOCATION;

ARCHITECTURAL CONSTRAINTS; GRAPH TRANSFORMATIONS; RECONFIGURABLE ARCHITECTURES; RUN-TIME RECONFIGURATION;

COMPUTER ARCHITECTURE;

EID: 33746156465     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FCCM.2005.28     Document Type: Conference Paper

References (4)

1. J. Noguera, R. M. Badia, Power-Performance trade-offs for reconfigurable computing", CODES+ISSS, 2004
2. H Quinn, L A Smith King, M Leeser, W Meleis, 'Runtime Assignment of Reconfigurable Hardware Components for Image Processing Pipelines", FCCM, 2003
3. S. Hauck, 'Configuration pre-fetch for single context reconfigurable processors", FPGA, 1998.
4. M. J. Wirthlin, "Improving functional density through Run-time Circuit, Reconfiguration", PhD Thesis, Electrical and Computer Engineering Dept, Brigham Young Univesity, 1997.