Scheduling divisible loads on partially reconfigurable hardware

Proceedings - 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2006

Volumn , Issue , 2006, Pages 289-290

  Vikram, K N ^a   Vasudevan, V ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY MADRAS   (India)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; CONSTRAINED OPTIMIZATION; PARALLEL PROCESSING SYSTEMS; RESOURCE ALLOCATION; SCHEDULING; TIME DELAY;

MULTIPLE PROCESSING UNITS (PU); RUN-TIME RECONFIGURATION DELAY;

PROGRAM PROCESSORS;

EID: 34547469578     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FCCM.2006.63     Document Type: Conference Paper

References (3)

1. G. D. Barlas. Collection-aware optimum sequencing of operations and closed-form solutions for the distribution of a divisible load on arbitrary processor trees. IEEE Trans. Parallel Distrib. Syst., 9(5):429-441, May 1998.
2. V. Bharadwaj, D. Ghose, V. Mani, and T. G. Robertazzi. Scheduling divisible loads in parallel and distributed systems. IEEE CS Press, Sept. 1996.
3. K. N. Vikram and V. Vasudevan. Mapping data-parallel tasks onto partially reconfigurable hybrid processor architectures. Accepted for publication in IEEE Trans. VLSI Syst.