HW/SW codesign techniques for dynamically reconfigurable architectures

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 10, Issue 4, 2002, Pages 399-415

  Noguera, Juanjo ^a   Badia, Rosa M ^b  

^a Dept of Research and Development   (Spain)

^b UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

Dynamic scheduling; Dynamically reconfigurable architectures; HW SW codesign; HW SW partitioning

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER HARDWARE; COMPUTER SOFTWARE; FORMAL LOGIC; SCHEDULING;

DYNAMIC SCHEDULING; DYNAMICALLY RECONFIGURABLE ARCHITECTURES; DYNAMICALLY RECONFIGURABLE LOGIC;

COMPUTER ARCHITECTURE;

EID: 0036705054     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2002.801575     Document Type: Article

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