Design on power-rail ESD clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-nm CMOS process

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 53, Issue 10, 2006, Pages 2187-2193

  Ker, Ming Dou ^a   Chen, Wen Yi ^a   Hsu, Kuo Chun ^a,b  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b Global Unichip   (Taiwan)

Author keywords

Electrostatic discharge (ESD); ESD protection circuit; High voltage tolerant; Power rail ESD clamp circuit; Substrate triggered technique

Indexed keywords

DESIGN FOR TESTABILITY; DETECTOR CIRCUITS; ELECTRIC DISCHARGES; ELECTROSTATICS; OVERVOLTAGE PROTECTION;

HIGH-VOLTAGE TOLERANT; POWER-RAIL ELECTROSTATIC DISCHARGE CLAMP CIRCUIT; SUBSTRATE-TRIGGERED TECHNIQUE;

CMOS INTEGRATED CIRCUITS;

EID: 33750401073     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2006.882818     Document Type: Article

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