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Volumn , Issue , 2004, Pages 112-115

A new output buffer for 3.3-V PCI-X application in a 0.13-μm 1/2.5-V CMOS process

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC CONVERTERS; ELECTRIC POTENTIAL; FABRICATION; TRANSISTORS;

EID: 14544281098     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (7)

References (11)
  • 4
    • 0038420756 scopus 로고    scopus 로고
    • Design of 2.5V/5V mixed-voltage CMOS I/O buffer with only thin oxide device and dynamic n-well bias circuit
    • M.-D. Ker and C.-S. Tsai, "Design of 2.5V/5V mixed-voltage CMOS I/O buffer with only thin oxide device and dynamic n-well bias circuit," in Proc. IEEE Int. Symp. Circuits and Systems, 2003, vol. 4, pp. 97-100.
    • (2003) Proc. IEEE Int. Symp. Circuits and Systems , vol.4 , pp. 97-100
    • Ker, M.-D.1    Tsai, C.-S.2
  • 5
    • 0342422528 scopus 로고    scopus 로고
    • A 1.9V I/O buffer with gate-oxide protection and dynamic bus termination for 400MHz UltraSparc microprocessor
    • G P. Singh and R. B. Salem, "A 1.9V I/O buffer with gate-oxide protection and dynamic bus termination for 400MHz UltraSparc microprocessor," in IEEE Int. Solid-State Circuits Dig. Tech. Papers, 1999, pp. 274-275.
    • (1999) IEEE Int. Solid-state Circuits Dig. Tech. Papers , pp. 274-275
    • Singh, G.P.1    Salem, R.B.2
  • 6
    • 0033281017 scopus 로고    scopus 로고
    • A high-voltage output buffer fabricated on a 2V CMOS technology
    • L. T. Clark, "A high-voltage output buffer fabricated on a 2V CMOS technology," in Proc. Symp. VLSI Circuits, 1999, pp. 61-62.
    • (1999) Proc. Symp. VLSI Circuits , pp. 61-62
    • Clark, L.T.1
  • 8
    • 0031210025 scopus 로고    scopus 로고
    • Circuit techniques for 1.5-V power supply flash memory
    • Aug.
    • N. Otsuka and M. A. Horowitz, "Circuit techniques for 1.5-V power supply flash memory," IEEE J. Solid-State Circuits, vol. 32, no. 8, pp. 1217-1230, Aug. 1997.
    • (1997) IEEE J. Solid-state Circuits , vol.32 , Issue.8 , pp. 1217-1230
    • Otsuka, N.1    Horowitz, M.A.2
  • 9
    • 0033714415 scopus 로고    scopus 로고
    • Level converter with high immunity to power-supply bouncing for high-speed sub-1-V LSIs
    • Y. Kanno, H. Mizuno, K. Tanaka, and T. Watanabe, "Level converter with high immunity to power-supply bouncing for high-speed sub-1-V LSIs," in Proc. Symp. VLSI Circuits, 2000, pp. 202-203.
    • (2000) Proc. Symp. VLSI Circuits , pp. 202-203
    • Kanno, Y.1    Mizuno, H.2    Tanaka, K.3    Watanabe, T.4
  • 11
    • 0034454866 scopus 로고    scopus 로고
    • A 0.13 μm CMOS technology with 93 nm lithography and Cu/low-k for high performance applications
    • K.-K. Young et al., "A 0.13 μm CMOS technology with 93 nm lithography and Cu/low-k for high performance applications," in IEDM Tech. Dig., 2000, pp. 563-566.
    • (2000) IEDM Tech. Dig. , pp. 563-566
    • Young, K.-K.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.