Design on power-rail ESD clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-NM CMOS process

IEEE International Reliability Physics Symposium Proceedings

Volumn , Issue , 2005, Pages 606-607

  Ker, Ming Dou ^a   Chen, Wen Yi ^a   Hsu, Kuo Chun ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CLAMP CIRCUITS; ESD ROBUSTNESS; GATE OXIDES; POWER RAIL;

CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; ELECTRIC POWER SYSTEMS; INTERFACES (MATERIALS); RELIABILITY; ROBUSTNESS (CONTROL SYSTEMS);

NETWORKS (CIRCUITS);

EID: 28744457291     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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2. T. Maloney and W. Kan, "Stacked PMOS clamps for high-voltage power supply protection," in Proc. EOS/ESD Symp., 1999, pp. 70-77.
3. S. S. Poon and T. Maloney, "New considerations for MOSFET power clamps," in Proc. EOS/ESD Symp., 2002, pp. 1-5.
4. L. R. Avery, "ESD protection for overvoltage friendly input/output circuits," U.S. Patent 5708550, Jan. 1998.
5. J. Watt, "Fast turn-on silicon controlled rectifier (SCR) for electrostatic discharge (ESD) protection," U.S. Patent 5825600, Oct. 1998.
6. E. R. Worley, C. T. Nguyen, R. A. Kjar, and M. R. Tennyson, "Method and apparatus for coupling multiple independent on-chip VDD busses to an ESD core clamp," U.S. Patent 5654862, Oct., 1996.
7. M.-D. Ker and K.-H. Lin, "Design on ESD protection scheme for IC with power-down-mode operation," IEEE J. Solid-State Circuits, vol. 39, pp. 1378-1382, 2004.